ISL6548A-6506EVAL1Z Intersil, ISL6548A-6506EVAL1Z Datasheet - Page 4

• Manufacturer Part Number: ISL6548A-6506EVAL1Z
• Description: EVALUATION BOARD ISL6548A-6506
• Manufacturer: Intersil

Specifications of ISL6548A-6506EVAL1Z

• Main Purpose: Special Purpose DC/DC, DDR Memory Supply
• Outputs And Type: 7, Non-Isolated
• Power - Output: 178W
• Voltage - Output: 1.8V, 3.3V, 5V, 1.5V, 1.2V, 2.5V, 0.9V
• Current - Output: 15A, 14A, 14A, 10A, 5A, 5A, 2A
• Voltage - Input: 3.3V, 5V, 12V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6506, ISL6548A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Switching: -

S3 to S0 State Transition
Figure 5 shows the transition from the S3 sleep state to the
S0 state. This transition is accomplished by returning the S3
switch to the ACTIVE position. Once the PGOOD signal has
been asserted, the V
beyond the S3 load limitations of 5VDUAL.
ACPI Start Up Timing
The ISL6506 and ISL6548A chipset were designed to work
in tandem to start up critical ACPI and Memory voltages
within a specific window of opportunity during the overall
start up or sleep recovery process of a typical motherboard.
Figure 6 shows a generic desktop sleep state to wake state
sequencing. At time T1, either the SLP_S3# or SLP_S5#
signal transitions HIGH, which is the signal to the system to
enter into the S0 state. At time T2, 10ns later, PS_ON, the
signal that commands the ATX supply to turn on, is forced
LOW. At time T3, the ATX rails have risen to 95% of their
targeted nominal levels. The time between T2 and T3 can be
between 100ms and 500ms. At time T4, the PWR_OK signal
from the ATX supply starts to rise. The time between T3 and
SLP_S5#
OR
SLP_S3#
PS_ON
+12V, 5V,
3.3V
PWR_OK
PWROK
PCIRST#
NOTE: ALL SIGNALS AT 500mV/DIV UNLESS OTHERWISE STATED
5V/DIV
V
FIGURE 6. GENERIC WAKEUP SEQUENCING
S5
FIGURE 5. S3 TO S0 STATE TRANSITION
T1 T2
V
V
V
V
DDQ_DDR
5V/DIV
DDQ_DDR
GMCH
TT_GMCH/CPU
TT_DDR
V
TIMEBASE: 20ms/DIV
S3
4
T3
rail can then be loaded
T4 T5 T6
(NOT TO SCALE)
V
5V/DIV
VIDPGD
V
Application Note 1285
DAC
T4 will also fall between 100ms and 500ms. At time T5, the
ATX PWR_OK signal has risen HIGH. This transition is
specified to be less than 10ms. At this point, the PWROK
signal from the GMCH is commanded HIGH. At time T6,
anywhere from 31 to 44 RTCs after PWROK has asserted
HIGH, the PCIRST# signal from the ICH asserts HIGH.
When PCIRST# asserts HIGH, bus traffic resumes and the
system is awake.
The ISL6506 and ISL6548A chipset bring all the ACPI rails
under their control into regulation between time T3 and T4.
This timing assures, even with minimum specified system
timings, that the regulators will have their inputs available
from the ATX supply and also that the output rails will be in
regulation and ready for bus traffic once PCIRST# asserts
HIGH.[4], [5]
Evaluation Board Design
The complete Bill of Material for the evaluation board can be
seen in “ISL6548A_6506EVAL1Z Bill of Material” on
page 12. This section gives an overview of the design
parameters and decisions made for each regulator.
ISL6506 Circuitry
The ISL6506 incorporates all the ACPI timing, control and
monitoring required for the 5VDUAL and 3.3VDUAL rails,
while maintaining a low component count. The Vishay
Si7840 was utilized for both N-Channel MOSFET pass
elements due to the low r
the packaging. Very little power is dissipated from the
MOSFET in this application. The P-Channel MOSFET, the
Vishay Si7483, was chosen for similar reasons.
The MOSFET thermal capabilities and it’s r
two major considerations when choosing a MOSFET as a
pass element for the 5VDUAL and 3.3VDUAL rails. The
maximum allowable temperature rise of the MOSFET is
used to calculate the maximum power that the MOSFET can
dissipate via the thermal resistance ratings of the FET. The
maximum r
by dividing the maximum allowable power dissipation of the
MOSFET by the square of the maximum load current that
will flow through the MOSFET. If the datasheet specified
r
calculated maximum r
be used safely in the application, provided proper layout
techniques for thermal dissipation are used.
ISL6548A Circuitry
V
The V
a 15A continuous output load while maintaining 1.8V.
Voltage excursions due to transient loading of 25A/µs were
to be no greater than 50mV with a full 15A load step.
In order to supply 15A of continuous current, two upper and
two lower MOSFETs were utilized. The part chosen for both
DS(ON)
DDQ_DDR
DDQ_DDR
of the MOSFET being considered is less than this
DS(ON)
SWITCHING REGULATOR
switching regulator was designed to handle
of the MOSFET can then be calculated
DS(ON)
DS(ON)
value, then the MOSFET can
and thermal capabilities of
DS(ON)
January 15, 2007
are the
AN1285.0