HW-SD1800A-DSP-SB-UNI-G Xilinx Inc, HW-SD1800A-DSP-SB-UNI-G Datasheet - Page 24

• Manufacturer Part Number: HW-SD1800A-DSP-SB-UNI-G
• Description: KIT DEVELOPMENT SPARTAN 3ADSP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr
• Type: DSPr

Specifications of HW-SD1800A-DSP-SB-UNI-G

• Contents: Development Platform, Power Supply and software
• Silicon Manufacturer: Xilinx
• Features: 10/100/1000 PHY, JTAG Programming And Configuration Port
• Silicon Family Name: Spartan-3A
• Silicon Core Number: 3SD1800A-FG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Spartan 3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1574; HW-SD1800A-DSP-DB-UNI-G; HW-SD1800A-DSP-DB-UNI-G; HW-SD1800A-DSP-SB-UNI-G

Functional Description
48
specification can serve a dual role. All the differential I/O signals can be configured as
either differential pairs or single-ended signals, as required by the end application. In
providing differential signaling, higher performance LVDS interfaces can be implemented
between the baseboard and EXP module. Connection to high speed A/Ds, D/As, and flat
panel displays are possible with this signaling configuration. Applications that require
single-ended signals only can use each differential pair as two single-ended signals, for a
total of 84 single-ended I/O per connector (168 total in the dual slot configuration).
Table 15: EXP Connector Signals
The Spartan-3A DSP FPGA user I/O pins that connect to the two EXP connectors are
shown in the following tables. The Samtec QTE connector plugs on the Spartan-3A DSP
Starter Platform (part number: QTE-060-09-F-D-A) mate with the Samtec QSE high-
performance receptacles (part number: QSE-060-01-F-D-A), located on the daughter card.
Samtec also provides several high-performance ribbon cables that will mate to the JX1 and
JX2 connectors.
Table 16: EXP Connector JX1 Pinout
EXPx_SE_IO
EXPx_SE_CLK_IN
EXPx_DIFF_p/n
EXPx_DIFF_CLK_IN_p/n
EXPx_DIFF_CLK_OUT_p/n
Pin No.
FPGA
A22
A20
D20
C22
C21
C20
B21
B20
-
-
-
-
-
Net Names
EXP1_SE_IO_0
EXP1_SE_IO_2
2.5V
EXP1_SE_IO_4
EXP1_SE_IO_6
2.5V
EXP1_SE_IO_8
EXP1_SE_IO_10
2.5V
EXP1_SE_IO_12
EXP1_SE_IO_14
2.5V
2.5V
Net Name
www.xilinx.com
Total
Single-ended I/O
Single-ended clock inputs
Differential I/O pairs
Differential clock input pair,
global
Differential clock output pairs
Signal Description
EXP Connector
Pin No. (JX1)
10
12
14
16
18
20
22
24
24
2
4
6
8
Spartan-3A DSP Starter Platform User Guide
13
15
17
19
21
23
23
11
1
3
5
7
9
EXP1_SE_IO_1
EXP1_SE_IO_3
2.5V
EXP1_SE_IO_5
EXP1_SE_IO_7
2.5V
EXP1_SE_IO_9
EXP1_SE_IO_11
2.5V
EXP1_SE_IO_13
EXP1_SE_IO_15
2.5V
2.5V
UG454 (v1.1) January 30, 2009
Quantity
Net Name
34
22
64
2
1
1
Quantity per
Dual Slot
168
68
44
4
2
2
Pin No.
FPGA
G20
G19
D23
D22
D21
C23
E21
B23
-
-
-
-
-
R