CY3684 Cypress Semiconductor Corp, CY3684 Datasheet - Page 13
![KIT DEVELOPMENT EZ-USB FX2LP](/photos/9/22/92290/cy3684_board1_sml.jpg)
CY3684
Manufacturer Part Number
CY3684
Description
KIT DEVELOPMENT EZ-USB FX2LP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FXr
Type
MCUr
Datasheet
1.CY3684.pdf
(28 pages)
Specifications of CY3684
Contents
2 Boards, Cables, CD
Silicon Manufacturer
Cypress
Application Sub Type
USB
Kit Application Type
Interface
Silicon Core Number
CY7C68013A-128AXC
Features
FX2LP Development Kit
Silicon Family Name
EZ-USB FX2LP
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CY7C68013A-128AC, CY7C64713-128AC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1677
CY3684
Q2204408
CY3684
Q2204408
3. ‘C2 Load’:
4.5 Interface Connectors
Six 20-pin headers P1-P6 on the EZ-USB Development Board have pins assigned to be compati-
ble with HP (Agilent) logic analyzers, as shown in Table 3. The slight bulge in the middle rows of
the table (pins 9 and 11) indicates the connector key.
The six headers P1-P6 serve three purposes.
Table 3 shows the logic analyzer pod pin designations. The EZ-USB signals on P1-P6 are
arranged to fulfill the following requirements:
EZ-USB Development Board
A “C2” load provides a method for loading the EZ-USB internal RAM with 8051 firmware
before enumeration. This ‘boot load’ mechanism allows EZ-USB to enumerate as a fully cus-
tom device, since the 8051 code handles enumeration using VID/PID values embedded in the
code.
At power-on, if the EZ-USB chip detects an EEPROM with the hex value ‘C2’ as its first byte,
it continues to load an EZ-USB configuration byte, followed by blocks of 8051 code. The last
byte loaded takes the 8051 out of reset.
This mode usually requires a large EEPROM, such as the 8 Kilobyte 24LC64.
•
•
•
NOTE: If an EEPROM is connected to the SCL and SDA lines, but does not contain 0xC0 or
0xC2 as its first byte, the loader reverts to case 1, ‘generic’. In other words, the boot loader
operates as though no EEPROM is connected. Once the 8051 is running, however, it has
full access to any connected EEPROM, since the 8051 I
dent of the boot load logic.
They mate with the proto-typing board supplied in the EZ-USB Development Kit.
They allow direct connection of HP (Agilent) Logic Analyzer pods (Agilent P/N 01650-
63203).
They allow general purpose probing by other logic analyzers or oscilloscopes.
SW2=ON, SW1=LARGE
CLK1
D14
D12
D10
D8
D6
D4
D2
D0
Agilent 01650-63203 Pod Pins
Table 3. Logic Analyzer Pinout
11
13
15
17
19
3
5
7
9
10
12
14
16
18
20
4
6
8
2
GND
D15
D13
D11
C controller is completely indepen-
D9
D7
D5
D3
D1
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