C8051T606DK Silicon Laboratories Inc, C8051T606DK Datasheet - Page 133
C8051T606DK
Manufacturer Part Number
C8051T606DK
Description
KIT DEVELOPMENT FOR C8051T606
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051T600EDB.pdf
(188 pages)
2.C8051T606TDB.pdf
(1 pages)
3.C8051T606DK.pdf
(16 pages)
4.C8051T606TDB.pdf
(14 pages)
Specifications of C8051T606DK
Contents
Board, Adapter, Cable, CD, Power Supply
Processor To Be Evaluated
C8051T606x
Interface Type
RS-232, USB
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T606
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1666
- C8051T600EDB PDF datasheet
- C8051T606TDB PDF datasheet #2
- C8051T606DK PDF datasheet #3
- C8051T606TDB PDF datasheet #4
- Current page: 133 of 188
- Download datasheet (898Kb)
23.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc-
tion bit (WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated
and the ACKRQ bit is set. The software must respond to the received slave address with an ACK or ignore
the received slave address with a NACK.
If the received slave address is ignored by software (by NACKing the address), slave interrupts will be
inhibited until the next START is detected. If the received slave address is acknowledged, zero or more
data bytes are received.
The ACKRQ bit is set to 1 and an interrupt is generated after each received byte. Software must write the
ACK bit at that time to ACK or NACK the received byte.
The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 23.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
that the ‘data byte transferred’ interrupts occur before the ACK.
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 23.7. Typical Slave Write Sequence
W
A
Data Byte
Rev. 1.2
Interrupt Locations
C8051T600/1/2/3/4/5/6
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
A
P
133
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