MC56F8006DEMO Freescale Semiconductor, MC56F8006DEMO Datasheet - Page 59

• Manufacturer Part Number: MC56F8006DEMO
• Description: DEMO BOARD FOR MC56F8006
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8006DEMO

• Contents: Board
• Processor To Be Evaluated: MC56F8006
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8006
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.13.3
Freescale Semiconductor
1
2
Pulse width of spikes that must be suppressed by the input filter
The master mode I
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
The maximum t
Bus free time between STOP and START condition
After this period, the first clock pulse is generated.
SCI receive
SCI receive
Set-up time for a repeated START condition
data pin
data pin
Hold time (repeated) START condition.
(Input)
(Input)
Inter-Integrated Circuit Interface (I
RXD
TXD
Data hold time for I
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
HIGH period of the SCL clock
HD; DAT
LOW period of the SCL clock
2
SCL Clock Frequency
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
Data set-up time
Characteristic
must be met only if the device does not stretch the LOW period (t
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
2
C bus devices
Figure 29. RXD Pulse Width
Figure 30. TXD Pulse Width
Table 30. I
RXD
TXD
PW
PW
2
C Timing
Symbol
t
t
t
t
t
SU; STO
HD; STA
SU; STA
HD; DAT
SU; DAT
2
t
t
f
t
HIGH
LOW
SCL
BUF
t
C) Timing
SP
t
t
r
f
Minimum
250
N/A
4.0
4.7
4.0
4.7
4.0
4.7
0
—
—
Standard Mode
0
1
LOW
) of the SCL signal.
Maximum
3.45
1000
100
300
N/A
—
—
—
—
—
—
—
2
Specifications
Unit
MHz
ns
ns
ns
ns
s
s
s
s
s
s
s
59