C8051F120-TB Silicon Laboratories Inc, C8051F120-TB Datasheet - Page 318

• Manufacturer Part Number: C8051F120-TB
• Description: BOARD PROTOTYPING W/C8051F120
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120-TB

• Contents: Board
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Kit Contents: Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
23.2.2. Capture Mode
In Capture Mode, Timer 2, 3, and 4 will operate as a 16-bit counter/timer with capture facility. When the
Timer External Enable bit (found in the TMRnCN register) is set to ‘1’, a high-to-low transition on the TnEX
input pin (Timer 3 shares the T2EX pin with Timer 2) causes the 16-bit value in the associated timer (THn,
TLn) to be loaded into the capture registers (RCAPnH, RCAPnL). If a capture is triggered in the counter/
timer, the Timer External Flag (TMRnCN.6) will be set to ‘1’ and an interrupt will occur if the interrupt is
enabled. See
figuration of interrupt sources.
As the 16-bit timer register increments and overflows TMRnH:TMRnL, the TFn Timer Overflow/Underflow
Flag (TMRnCN.7) is set to ‘1’ and an interrupt will occur if the interrupt is enabled. The timer can be config-
ured to count down by setting the Decrement Enable Bit (TMRnCF.0) to ‘1’. This will cause the timer to
decrement with every timer clock/count event and underflow when the timer transitions from 0x0000 to
0xFFFF. Just as in overflows, the Overflow/Underflow Flag (TFn) will be set to ‘1’, and an interrupt will
occur if enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RLn
(TMRnCN.0) and the Timer 2, 3, and 4 Run Control bit TRn (TMRnCN.2) to logic 1. The Timer 2, 3, and 4
respective External Enable EXENn (TMRnCN.3) must also be set to logic 1 to enable captures. If EXENn
is cleared, transitions on TnEX will be ignored.
318
External Clock
SYSCLK
(XTAL1)
Tn
TnE
X
Section “11.3. Interrupt Handler” on page 154
Crossbar
8
Figure 23.4. T2, 3, and 4 Capture Mode Block Diagram
2
12
Crossbar
EXENn
TRn
0
1
TMRnCF
M
T
n
1
M
T
n
0
O
G
T
n
Rev. 1.4
O
T
n
E
TCLK
D
C
E
n
RCAPnL
TMRnL
0xFF
for further information concerning the con-
RCAPnH
TMRnH
0xFF
Toggle Logic
CP/RLn
EXENn
EXFn
C/Tn
TRn
TFn
0
1
Interrupt
(Port Pin)
Tn