C8051F410-TB Silicon Laboratories Inc, C8051F410-TB Datasheet - Page 157

• Manufacturer Part Number: C8051F410-TB
• Description: BOARD PROTOTYPING W/C8051F410
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410-TB

• Contents: Board
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F410
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bits7–0: P0MAT[7:0]: Port0 Match Value.
Bits7–0: P0MASK[7:0]: Port0 Mask Value.
Bits7–0: High Impedance Overdrive Mode Enable Bits for P0.7–P0.0 (respectively).
R/W
R/W
R/W
Bit7
Bit7
Bit7
These bits control the value that unmasked P0 Port pins are compared against. A Port
Match event is generated if (P0 & P0MASK) does not equal (P0MAT & P0MASK).
These bits select which Port pins will be compared to the value stored in P0MAT.
0: Corresponding P0.n pin is ignored and cannot cause a Port Match event.
1: Corresponding P0.n pin is compared to the corresponding bit in P0MAT.
Port pins configured to High-Impedance Overdrive Mode do not require additional overdrive
current, although selecting this mode results in a slight increase in supply current. Port pins
configured to Normal Overdrive Mode require approximately 150 µA of input overdrive cur-
rent when the voltage at the pin reaches V
0: Corresponding P0.n pin is configured to Normal Overdrive Mode.
1: Corresponding P0.n pin is configured to High-Impedance Overdrive Mode.
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 18.9. P0ODEN: Port0 Overdrive Mode
SFR Definition 18.8. P0MASK: Port0 Mask
SFR Definition 18.7. P0MAT: Port0 Match
R/W
R/W
R/W
Bit5
Bit5
Bit5
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.1
R/W
R/W
R/W
Bit3
Bit3
Bit3
IO
+0.7 V.
R/W
R/W
R/W
Bit2
Bit2
Bit2
C8051F410/1/2/3
R/W
R/W
R/W
Bit1
Bit1
Bit1
SFR Address:
SFR Address:
SFR Address:
R/W
R/W
Bit0
R/W
Bit0
Bit0
0xD7
0xB0
0xC7
00000000
Reset Value
Reset Value
00000000
Reset Value
11111111
157