C8051F410-TB Silicon Laboratories Inc, C8051F410-TB Datasheet - Page 162
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C8051F410-TB
Manufacturer Part Number
C8051F410-TB
Description
BOARD PROTOTYPING W/C8051F410
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F410-TB
Contents
Board
Processor To Be Evaluated
C8051F41x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F410
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F410/1/2/3
162
Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in regis-
Bits7–0: P2SKIP[7:0]: Port2 Crossbar Skip Enable Bits.
R/W
Bit7
Bit7
R
ter P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (V
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
R/W
Bit6
Bit6
R
SFR Definition 18.18. P2MDOUT: Port2 Output Mode
SFR Definition 18.19. P2SKIP: Port2 Skip
R/W
Bit5
Bit5
R
R/W
Bit4
Bit4
R
Rev. 1.1
R/W
Bit3
Bit3
R
R/W
Bit2
Bit2
R
R/W
Bit1
Bit1
R
REF
SFR Address:
SFR Address:
input, external oscil-
R/W
R/W
Bit0
Bit0
0xA6
0xD6
00000000
00000000
Reset Value
Reset Value
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