MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 3

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 1
1
Freescale Semiconductor
MMC
SD
shows the major functional units within the MPC8536E.
Performance
Pin Assignments and Reset States
Device
Host/
ULPI
USB
Monitor
Timers
MPC8536E
The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails
for the eTSEC blocks and to ease the port of existing PowerQUICC III software
The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR
configuration. Please refer to
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Device
Host/
ULPI
USB
Enhanced
Local Bus
Device
Host/
ULPI
USB
Figure 1. MPC8536E Block Diagram
SEC
SATA
Table 1
32-Kbyte
D-Cache
e500 Core
OpenPIC
SATA
for more details.
NOTE
NOTE
2 Lane SERDES
32-Kbyte
I-Cache
w/ IEEE 1588
Ethernet
SGMII
Gigabit
Coherency
Module
512-Kbyte
L2 Cache
w/ IEEE 1588
Ethernet
SGMII
Gigabit
DUART
2x I
eSPI
2
C
Management
Queue
Async
PCI 32
PCI-e
Power
8 Lane SERDES
SDRAM Controller
PCI-e
DDR2/DDR3
with ECC
64-bit
PCI-e
DMA
3

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