HW-V5-ML510-G Xilinx Inc, HW-V5-ML510-G Datasheet - Page 25

• Manufacturer Part Number: HW-V5-ML510-G
• Description: BOARD EVAL FOR VIRTEX-5 ML510
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-ML510-G

• Contents: Evaluation Board
• Kit Contents: ML510 Board (ATX Form Factor), 512 MB CompactFlash Card, Two 512 MB DDR2 DIMMs, LCD Display, Cable
• Svhc: No SVHC (15-Dec-2010)
• Development Tool Type: Hardware / Software - Dev Kit
• Silicon Manufacturer: Xilinx
• Core Architecture: Virtex
• Silicon Family Name: Virtex-5
• Features: VGA Graphics Interface, Fan
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 47: GTX_DUAL Tile Receiver Switching Characteristics (Cont’d)
CRC Block Switching Characteristics
Table 48: CRC Block Switching Characteristics
Ethernet MAC Switching Characteristics
Consult UG194: Virtex-5 FPGA Tri-mode Ethernet Media Access Controller User Guide for further information.
Table 49: Maximum Ethernet MAC Performance
Endpoint Block for PCI Express Designs Switching Characteristics
Consult UG197: Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide for further information.
Table 50: Maximum Performance for PCI Express Designs
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
7.
SJ Jitter Tolerance with Stressed Eye
F
F
F
F
F
CRC
TEMACCLIENT
TEMACPHY
PCIECORE
PCIEUSER
Symbol
Symbol
Symbol
Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
All jitter values are based on a Bit Error Ratio of 1e
Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
PLL frequency at 1.6 GHz and OUTDIV = 1.
GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
Composite jitter with RX equalizer enabled. DFE disabled.
JT_SJSE
JT_TJSE
JT_SJ
JT_SJ
Symbol
750
150
4.25
4.25
Client interface maximum frequency
Physical interface maximum frequency
Core clock maximum frequency
User clock maximum frequency
CRCCLK maximum frequency
Sinusoidal Jitter
Sinusoidal Jitter
Total Jitter with Stressed
Eye
Sinusoidal Jitter with
Stressed Eye
(7)
Description
(7)
(3)
(4)(6)
(4)(6)
Description
Description
–12
Description
.
750 Mb/s
150 Mb/s
4.25 Gb/s
4.25 Gb/s
www.xilinx.com
10 Mb/s – 8-bit width
100 Mb/s – 8-bit width
1000 Mb/s – 8-bit width
2000 Mb/s – 16-bit width
100 Mb/s – 4-bit width
1000 Mb/s – 8-bit width
2000 Mb/s – 8-bit width
10 Mb/s – 4-bit width
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Conditions
1.25
12.5
325
250
250
125
125
125
250
2.5
25
-3
-3
-3
0.57
0.57
0.69
Min
0.1
Speed Grade
Speed Grade
Speed Grade
1.25
12.5
250
250
325
125
125
125
250
Typ
2.5
25
-2
-2
-2
Max
1.25
12.5
250
250
270
125
125
125
250
2.5
25
-1
-1
-1
Units
Units
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
UI
UI
UI
UI
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