HW-V5-ML510-G Xilinx Inc, HW-V5-ML510-G Datasheet - Page 51

• Manufacturer Part Number: HW-V5-ML510-G
• Description: BOARD EVAL FOR VIRTEX-5 ML510
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-ML510-G

• Contents: Evaluation Board
• Kit Contents: ML510 Board (ATX Form Factor), 512 MB CompactFlash Card, Two 512 MB DDR2 DIMMs, LCD Display, Cable
• Svhc: No SVHC (15-Dec-2010)
• Development Tool Type: Hardware / Software - Dev Kit
• Silicon Manufacturer: Xilinx
• Core Architecture: Virtex
• Silicon Family Name: Virtex-5
• Features: VGA Graphics Interface, Fan
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Configuration Switching Characteristics
Table 70: Configuration Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Power-up Timing Characteristics
T
T
T
T
Master/Slave Serial Mode Programming Switching
T
T
T
F
F
F
SelectMAP Mode Programming Switching
T
T
T
T
T
T
F
F
F
Boundary-Scan Port Timing Specifications
T
T
T
F
F
PL
POR
ICCK
PROGRAM
DCCK
DSCCK
CCO
MCCK
MCCKTOL
MSCCK
SMDCCK
SMCSCCK
SMCCKW
SMCKCSO
SMCO
SMCKBY
SMCCK
RBCCK
MCCKTOL
TAPTCK
TCKTAP
TCKTDO
TCK
TCKB
/T
/T
CCKD
/T
/T
SCCKD
/T
SMCCKD
SMWCCK
SMCCKCS
Symbol
Program Latency
Power-on-Reset
CCLK (output) delay
Program Pulse Width
DIN Setup/Hold, slave mode
DIN Setup/Hold, master mode
DOUT
Maximum Frequency, master mode with
respect to nominal CCLK.
Frequency Tolerance, master mode with
respect to nominal CCLK.
Slave mode external CCLK
SelectMAP Data Setup/Hold
CS_B Setup/Hold
RDWR_B Setup/Hold
CSO_B clock to out
(330 Ω pull-up resistor required)
CCLK to DATA out in readback
CCLK to BUSY out in readback
Maximum Frequency with respect to nominal
CCLK.
Maximum Readback Frequency with respect
to nominal CCLK
Frequency Tolerance with respect to nominal
CCLK.
TMS and TDI Setup time before TCK
TMS and TDI Hold time after TCK
TCK falling edge to TDO output valid
Maximum configuration TCK clock frequency
Maximum boundary-scan TCK clock
frequency
(1)
(1)
Description
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
400
250
100
±50
100
100
±50
4.0
0.0
4.0
0.0
7.5
3.0
0.5
3.0
0.5
8.0
0.5
7.5
9.0
1.0
2.0
10
50
10
60
66
66
-3
3
6
Speed Grade
400
250
100
±50
100
100
±50
4.0
0.0
4.0
0.0
7.5
3.0
0.5
3.0
0.5
8.0
0.5
9.0
7.5
1.0
2.0
10
50
10
60
66
66
-2
3
6
400
250
100
±50
100
100
±50
4.0
0.0
4.0
0.0
7.5
3.0
0.5
3.0
0.5
8.0
0.5
9.0
7.5
1.0
2.0
10
50
10
60
66
66
-1
3
6
ms, Min/Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
ms, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz,
MHz
Max
%
%
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