8.12.00 J-LINK ARM-PRO Segger Microcontroller Systems, 8.12.00 J-LINK ARM-PRO Datasheet - Page 121

• Manufacturer Part Number: 8.12.00 J-LINK ARM-PRO
• Description: JTAG EMULATOR USB ETHERNET ARM
• Manufacturer: Segger Microcontroller Systems
• Type: Emulatorr

Specifications of 8.12.00 J-LINK ARM-PRO

• Contents: Emulation Module
• For Use With/related Products: ARM7, ARM9, ARM11, Cortex
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8.12.00 J-LINK ARM-PRO; 899-1007

5.8.2.6 Type 5: Reset core & peripherals, halt before bootloader
5.8.2.7 Type 6: Reset for Freescale Kinetis devices
5.8.2.8 Type 7: Reset for Analog Devices CPUs (ADI Halt after kernel)
5.8.2.9 Type 9: Reset for LPC1200 devices
5.8.2.10 Type 10: Reset for Samsung S3FN60D devices
J-Link / J-Trace (UM08001)
Same as Type 0, but bootloader is never executed. Not normally used, except in situ-
ations where the bootloader needs to be debugged.
Performs a via reset strategy 0 (normal) first in order to reset the core & peripherals
and halt the CPU immediately after reset. After the CPU is halted, the watchdog is
disabled, since the watchdog is running after reset by default and if the target appli-
cation does not feed the watchdog, J-Link loses connection to the device since it is
reset permanently.
Performs a reset of the core and peripherals by setting the SYSRESETREQ bit in the
AIRCR. The core is allowed to perform the ADI kernel (which enables the debug inter-
face) but the core is halted before the first instruction after the kernel is executed in
order to guarantee that no user application code is performed after reset.
Type 8: Reset core and peripherals
J-Link tries to reset both, core and peripherals by setting the SYSRESETREQ bit in the
AIRCR. The VC_CORERESET bit is used to halt the CPU before it executes a single
instruction.
On the NXP LPC1200 devices the watchdog is enabled after reset and not disabled by
the bootloader, if a valid application is in the flash memory. Moreover, the watchdog
keeps counting if the CPU is in debug mode. When using this reset strategy, J-Link
performs a reset of the CPU and peripherals, using the SYSRESETREQ bit in the
AIRCR and halts the CPU after the bootloader has been performed and before the
first instruction of the user code is executed. Then the watchdog of the LPC1200
device is disabled. This reset strategy is only guaranteed to work on "modern" J-
Links (J-Link V8, J-Link Pro, J-Link Ultra, J-Trace for Cortex-M, J-Link Lite) and if a
SWD speed of min. 1 MHz is used. This reset strategy should also work for J-Links
with hardware version 6, but it can not be guaranteed that these J-Links are always
fast enough in disabling the watchdog.
On the Samsung S3FN60D devices the watchdog may be running after reset (if the
watchdog is active after reset or not depends on content of the smart option bytes at
addr 0xC0). The watchdog keeps counting even if the CPU is in debug mode (e.g.
halted by a halt request or halted by vector catch). When using this reset strategy, J-
Link performs a reset of the CPU and peripherals, using the SYSRESETREQ bit and
sets VC_CORERESET in order to halt the CPU after reset, before it executes a single
instruction. Then the watchdog of the S3FN60D device is disabled.
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