M3062PT3-CPE-2 Renesas Electronics America, M3062PT3-CPE-2 Datasheet - Page 86

• Manufacturer Part Number: M3062PT3-CPE-2
• Description: EMULATOR COMPACT M16C/26A,28,29
• Manufacturer: Renesas Electronics America
• Type: In Circuit Debuggerr

Specifications of M3062PT3-CPE-2

• Contents: Compact Emulator, IDE, Assembler and Linker
• For Use With/related Products: M16C/26A, M16C/28, M16C/29
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

M3062PT3-CPE User’s Manual
(2) Multiplex Bus Timing
Table 4.6 and Figure 4.5 show the bus timing in memory expansion mode and microprocessor mode (2 wait, accessing external
area, using multiplex bus).
Table 4.6 Memory expansion mode and microprocessor mode (2 wait, accessing external area, using multiplex bus)
*1 Calculated by the following formula according to the frequency of BCLK.
*2 Calculated by the following formula according to the frequency of BCLK.
*3 Calculated by the following formula according to the frequency of BCLK.
*4 Calculated by the following formula according to the frequency of BCLK.
REJ10J1007-0400 Rev.4.00 July 29, 2009
(
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdz(RD-AD)
f
f
f
0
n
0
0
(
(
(
5 .
5 .
5 .
f
−
BCLK
BCLK
BCLK
(
×
×
×
0
BCLK
Symbol
5 .
10
10
10
)
9
9
9
×
)
)
)
10
−
−
)
15
9
[ns]
40
−
50
[ns]
[ns]
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select output delay time
Chip-select output hold time (BCLK standard)
Chip-select output hold time (RD standard)
Chip-select output hold time (WR standard)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
ALE output delay time (BCLK standard)
ALE output hold time (BCLK standard)
ALE output delay time (Address standard)
ALE output hold time (Address standard)
After address RD signal output delay time
After address WR signal output delay time
Address output floating start time
[ns] n: "2" for 2 wait
Item
Min.
(*1)
(*1)
(*1)
(*1)
(*2)
(*1)
(*3)
30
-4
Actual MCU
4
4
0
0
4
0
0
[ns]
Max.
50
50
40
40
50
40
8
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4. Hardware Specifications
Min.
(*4)
(*4)
(*4)
(*4)
(*4)
-10
-10
This product
[ns]
See left
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Page 84 of 108
Max.
15