E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 24

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11.2 Register Descriptions ........................................................................................................ 523
11.3 Operation .......................................................................................................................... 534
11.4 Usage Notes ...................................................................................................................... 543
Section 12 8-Bit Timers
12.1 Overview........................................................................................................................... 545
12.2 Register Descriptions ........................................................................................................ 548
12.3 Operation .......................................................................................................................... 556
Rev. 5.00 Sep 14, 2006 page xxii of xxviii
11.1.3 Pin Configuration................................................................................................. 521
11.1.4 Registers............................................................................................................... 522
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 523
11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 524
11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 525
11.2.4 Notes on NDR Access.......................................................................................... 525
11.2.5 PPG Output Control Register (PCR).................................................................... 528
11.2.6 PPG Output Mode Register (PMR)...................................................................... 529
11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 532
11.2.8 Port 2 Data Direction Register (P2DDR)............................................................. 532
11.2.9 Module Stop Control Register (MSTPCR) .......................................................... 533
11.3.1 Overview.............................................................................................................. 534
11.3.2 Output Timing...................................................................................................... 535
11.3.3 Normal Pulse Output............................................................................................ 536
11.3.4 Non-Overlapping Pulse Output............................................................................ 538
11.3.5 Inverted Pulse Output .......................................................................................... 541
11.3.6 Pulse Output Triggered by Input Capture ............................................................ 542
11.4.1 Operation of Pulse Output Pins............................................................................ 543
11.4.2 Note on Non-Overlapping Output........................................................................ 543
12.1.1 Features................................................................................................................ 545
12.1.2 Block Diagram ..................................................................................................... 546
12.1.3 Pin Configuration................................................................................................. 547
12.1.4 Register Configuration......................................................................................... 547
12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ......................................................... 548
12.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ............................... 548
12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) ................................ 549
12.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) .................................................. 549
12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 552
12.2.6 Module Stop Control Register (MSTPCR) .......................................................... 555
12.3.1 TCNT Incrementation Timing ............................................................................. 556
12.3.2 Compare Match Timing....................................................................................... 557
12.3.3 Timing of External RESET on TCNT ................................................................. 559
12.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 559
..................................................................................................... 545