E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 57

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E62655RUSB

Manufacturer Part Number
E62655RUSB
Description
EMULATOR BASE H8S/2655R W/USB
Manufacturer
Renesas Electronics America
Type
Microcontrollerr
Datasheet

Specifications of E62655RUSB

Contents
E6000 Emulator Unit and 4 Logic Probes
For Use With/related Products
H8S/2655R
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area
starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16
bits (figure 2.2). The exception vector table differs depending on the microcontroller. For details
of the exception vector table, see section 4, Exception Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-
bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note
that this area is also used for the exception vector table.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Figure 2.2 Exception Vector Table (Normal Mode)
Power-on reset exception vector
Manual reset exception vector
(Reserved for system use)
Exception vector 1
Exception vector 2
Rev. 5.00 Sep 14, 2006 page 27 of 1060
Exception
vector table
REJ09B0331-0500
Section 2 CPU

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