AD9380/PCB Analog Devices Inc, AD9380/PCB Datasheet - Page 21

• Manufacturer Part Number: AD9380/PCB
• Description: BOARD EVALUATION FOR AD9380
• Manufacturer: Analog Devices Inc

Specifications of AD9380/PCB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

R
B
G
Color Space Conversion (CSC) Matrix
The CSC matrix in the AD9380 consists of three identical
processing channels. In each channel, three input values are
multiplied by three separate coefficients. Also included are an
offset value for each row of the matrix and a scaling multiple
for all values. Each value has a 13-bit, twos complement
resolution to ensure the signal integrity is maintained. The
CSC is designed to run at speeds up to 150 MHz, supporting
resolutions up to 1080p at 60 Hz. With any-to-any color space
support, formats such as RGB, YUV, YCbCr, and others are
supported by the CSC.
The main inputs, R
inputs from each channel. These inputs are based on the input
format detailed in Table 11 The mapping of these inputs to the
CSC inputs is shown in Table 10.
Table 10. CSC Port Mapping
Input Channel
R/CR
Gr/Y
B/CB
One of the three channels is represented in Figure 13. In each
processing channel, the three inputs are multiplied by three
separate coefficients marked a1, a2, and a3. These coefficients
are divided by 4096 to obtain nominal values ranging from
–0.9998 to +0.9998. The variable labeled a4 is used as an offset
control. The CSC_Mode setting is the same for all three
processing channels. This multiplies all coefficients and offsets
by a factor of 2
The functional diagram for a single channel of the CSC, as
shown in Figure 13, is repeated for the remaining G and B
channels. The coefficients for these channels are b1, b2, b3, b4,
c1, c2, c3, and c4.
A programming example and register settings for several
common conversions are listed in the Color Space Converter
(CSC) Common Settings section.
For a detailed functional description and more programming
examples, refer to Application Note
Space Converter User's Guide.
IN
IN
IN
[11:0]
[11:0]
[11:0]
a1[12:0]
a2[12:0]
a3[12:0]
×
×
×
CSC_Mode
×
×
×
IN
4096
4096
4096
Figure 13. Single CSC Channel
1
, G
1
1
.
IN
, and B
+
IN
+
CSC Input Channel
R
G
B
come from the 8- to 12-bit
IN
IN
B
IN
AN-795, AD9880 Color
a4[12:0]
+
×4
×2
CSC_Mode[1:0]
2
1
0
R
OUT
[11:0]
Rev. 0 | Page 21 of 60
AUDIO PLL SETUP
Data contained in the audio infoframes, among other registers,
define for the AD9380 HDMI receiver not only the type of
audio, but the sample frequency. It also contains information
about the N and CTS values used to re-create the clock. With
this information, it is possible to regenerate the audio sampling
frequency. The audio clock is regenerated by dividing the 20-bit
CTS value into the TMDS clock, then multiplying by the 20-bit
N value. This yields a multiple of the sampling frequency (f
either 128 × f
up to 1024 × f
AUDIO BOARD LEVEL MUTING
The audio can be muted through the infoframes or locally
via the serial bus registers. Muting can be controlled with
Register R0x57, Bits [7:4].
AVI Infoframes
The HDMI TMDS transmission contains infoframes with
specific information for the monitor such as:
•
•
•
•
•
•
•
128 ×
1
CLOCK
N AND CTS VALUES ARE TRANSMITTED USING THE
AUDIO CLOCK REGENERATION PACKET. VIDEO
CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.
VIDEO
N
Audio information
o
o
o
Speaker placement
N and CTS values (for reconstruction of the audio)
Muting
Source information
o
o
o
Video information
o
o
o
o
o
Vendor (transmitter source) name and product model
f
S
2 to 8 channels of audio identified
Audio coding
Audio sampling frequency
CD
SACD
DVD
Video ID Code (per CEA861B)
Color space
Aspect ratio
Horizontal and vertical bar information
MPEG frame information (I, B, or P frame)
REGISTER
DIVIDE
S
SOURCE DEVICE
S
BY
or 256 × f
.
N
N
Figure 14. N and CTS for Audio Clock
COUNTER
CYCLE
TIME
S
. It is possible for this to be specified
CLOCK
TMDS
CTS
N
1
1
DIVIDE
CTS
BY
SINK DEVICE
MULTIPLY
BY
N
AD9380
128 ×
S
) of
f
S