HS7750KCI01H Renesas Electronics America, HS7750KCI01H Datasheet - Page 218

• Manufacturer Part Number: HS7750KCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7750KCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6.6
Break Condition
Sequential break condition 2-1
Sequential break condition 3-2-1
Sequential break condition 4-3-2-1
Note: Sequential breaks can be specified by the [Configuration] dialog box.
Notes on Setting the [Break Condition] Dialog Box and BREAKCONDITION_SET
Command:
1. When [Go to cursor], [Step In], [Step Over], or [Step Out] is selected, the settings of Break
2. Break Condition 4 is disabled when an instruction to which a BREAKPOINT has been set is
3. When a Break Condition is satisfied, emulation may stop after two or more instructions have
4. If a PC break before execution is set to the slot instruction after a delayed branch instruction,
6.5.3
1. When an odd address is set, the next lowest even address is used.
2. A BREAKPOINT is accomplished by replacing instructions. Accordingly, it can be set only
3. During step execution, a BREAKPOINT is disabled.
Rev. 2.0, 01/01, page 194 of 214
Condition 4 are disabled.
executed. Accordingly, do not set a BREAKPOINT to an instruction which satisfies Break
Condition 4.
been executed.
user program execution cannot be terminated before the slot instruction execution; execution
stops before the branch destination instruction.
to the internal RAM area. However, a BREAKPOINT cannot be set to the following
addresses:
In addition, do not perform memory write, BREAKPOINT, or download even if the memory
space can only be written by the MMU.
An address whose memory content is H'003B
An area other than the CS0 to CS6 areas and the internal RAM area
An instruction in which Break Condition 4 is satisfied
A slot instruction of a delayed branch instruction
Notes on Setting the [Breakpoint] Dialog Box
Sequential Break Conditions
Description
Program is halted when Break Condition 2 and Break
Condition 1 are satisfied in that order.
Program is halted when Break Condition 3, Break Condition
2, and Break Condition 1 are satisfied in that order.
3, Break Condition 2, and Break Condition 1 are satisfied in
that order.
Program is halted when Break Condition 4, Break Condition