74aup1g332 NXP Semiconductors, 74aup1g332 Datasheet
74aup1g332
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74aup1g332 Summary of contents
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... Low-power 3-input OR gate Rev. 01 — 13 November 2006 1. General description The 74AUP1G332 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V ...
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... Type number Package Temperature range Name 74AUP1G332GW +125 C 74AUP1G332GM +125 C 74AUP1G332GF +125 C 4. Marking Table 2. Marking Type number 74AUP1G332GW 74AUP1G332GM 74AUP1G332GF 5. Functional diagram 001aad933 Fig 1. Logic symbol Fig 3. Logic diagram 74AUP1G332_1 Product data sheet Description SC-88 plastic surface-mounted package ...
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... 001aad931 Transparent top view Fig 5. Pin configuration SOT886 (XSON6 Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate 74AUP1G332 GND 001aad932 Transparent top view Fig 6. Pin configuration SOT891 (XSON6) ...
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... Active mode and Power-down mode +125 C amb derates linearly with 4.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode Power-down mode 0 3 Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate Min Max 0.5 +4 [1] 0.5 +4 [1] 0.5 +4 ...
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... GND GND GND Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate Min Typ Max ...
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... GND Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate Min Typ Max ...
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... 3 0 GND GND. CC Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate Min Typ Max ...
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... [2] Figure Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate Figure +125 C [1] Typ Max Min ( 17 2.3 5.2 10.2 2.0 1.7 3.7 6.0 1.9 1.6 3.0 4.7 1.4 1.4 2.3 3.3 1 ...
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... where input V M GND t PHL output Table 9. Input 0 Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate +125 C [1] Typ Max Min Max ( ...
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... PULSE DUT GENERATOR [ open = for measuring propagation delays, setup and hold times and pulse width R L Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate V EXT 001aac521 of the pulse generator. o EXT , ...
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... scale 2.2 1.35 2.2 1.3 0.65 1.8 1.15 2.0 REFERENCES JEDEC JEITA SC-88 Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate detail 0.45 0.25 0.2 0.2 0.1 0.15 0.15 EUROPEAN PROJECTION SOT363 ISSUE DATE 04-11-08 06-03-16 © NXP B.V. 2006. All rights reserved. ...
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... Product data sheet scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate 4 ( EUROPEAN PROJECTION SOT886 ISSUE DATE 04-07-15 04-07-22 © NXP B.V. 2006. All rights reserved ...
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... Product data sheet scale 1.05 0.35 0.40 0.55 0.35 0.95 0.27 0.32 REFERENCES JEDEC JEITA Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate SOT891 2 mm EUROPEAN ISSUE DATE PROJECTION 05-03-11 05-04-06 © NXP B.V. 2006. All rights reserved ...
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... TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74AUP1G332_1 20061113 74AUP1G332_1 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate Supersedes - © NXP B.V. 2006. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 13 November 2006 74AUP1G332 Low-power 3-input OR gate © NXP B.V. 2006. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 13 November 2006 Document identifier: 74AUP1G332_1 ...