ADC122S706EB/NOPB National Semiconductor, ADC122S706EB/NOPB Datasheet
ADC122S706EB/NOPB
Specifications of ADC122S706EB/NOPB
Related parts for ADC122S706EB/NOPB
ADC122S706EB/NOPB Summary of contents
Page 1
... MHz to 16 MHz. The ADC122S706 is available in a 14-lead TSSOP package. Connection Diagram TRI-STATE® trademark of National Semiconductor Corporation. MICROWIRE™ trademark of National Semiconductor Corporation. QSPI™ and SPI™ are trademarks of Motorola, Inc. ...
Page 2
Ordering Information Order Code Temperature Range ADC122S706CIMT −40°C to +105°C ADC122S706CIMTX −40°C to +105°C ADC122S706EB Block Diagram www.national.com Description 14-Lead TSSOP Package, 1000 Units Tape & Reel 14-Lead TSSOP Package, 3500 Units Tape & Reel Evaluation Board 2 Top Mark ...
Page 3
Pin Descriptions and Equivalent Circuits Pin No. Symbol V 1 REF 2 CHA+ 3 CHA− 4 GND 5 CHB− 6 CHB DUAL 9 GND OUTA 12 D OUTB 13 SCLK 14 ...
Page 4
... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage V A Digital Supply Voltage V D Voltage on Any Pin to GND Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Consumption 25° ...
Page 5
Symbol Parameter CMRR Common Mode Rejection Ratio V Reference Voltage Range REF DIGITAL INPUT CHARACTERISTICS V Input High Voltage IH V Input Low Voltage IL I Input Current (Note 11 Input Capacitance IND DIGITAL OUTPUT CHARACTERISTICS V Output ...
Page 6
Symbol Parameter Power Consumption, Continuously Converting (Dual Data Output Mode) PWR (Conv) Power Consumption, Continuously Converting (Single Data Output Mode) PWR Power Consumption, Power Down Mode (PD) (CS high) PSRR Power Supply Rejection Ratio AC ELECTRICAL CHARACTERISTICS f Maximum Clock ...
Page 7
ADC122S706 Timing Specifications The following specifications apply for V unless otherwise noted. Boldface limits apply for T Symbol Parameter t CS Setup Time prior to an SCLK rising edge CSSU t D Enable Time after the falling edge of CS ...
Page 8
Timing Diagrams FIGURE 1. ADC122S706 Single Conversion Timing Diagram (DUAL Data Output Mode) FIGURE 2. ADC122S706 Single Conversion Timing Diagram (SINGLE Data Output Mode) www.national.com 8 30017101 30017142 ...
Page 9
FIGURE 3. ADC122S706 Continuous Conversion Timing Diagram (DUAL Data Output Mode) FIGURE 4. D Rise and Fall Times OUT 30017111 FIGURE 5. D Hold and Access Times OUT 30017110 FIGURE 6. Valid CS Assertion Times 30017106 FIGURE 7. Voltage Waveform ...
Page 10
Specification Definitions APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is acquired or held for conversion. COMMON MODE REJECTION RATIO (CMRR measure of how well in-phase signals ...
Page 11
Typical Performance Characteristics MHz, DUAL = 100 kHz unless otherwise stated. SCLK D IN DNL - 1 MSPS DNL vs DNL vs. V REF 5.0V ...
Page 12
Typical Performance Characteristics MHz, DUAL = 100 kHz unless otherwise stated. SCLK D IN DNL vs. SCLK FREQUENCY DNL vs. TEMPERATURE SINAD vs. V www.national.com 5.0V ...
Page 13
Typical Performance Characteristics MHz, DUAL = 100 kHz unless otherwise stated. SCLK D IN SINAD vs. V REF SINAD vs. SCLK FREQUENCY SINAD vs. INPUT FREQUENCY 5.0V ...
Page 14
Typical Performance Characteristics MHz, DUAL = 100 kHz unless otherwise stated. SCLK D IN SINAD vs. TEMPERATURE V CURRENT vs CURRENT vs. TEMPERATURE A www.national.com 5.0V, ...
Page 15
Typical Performance Characteristics MHz, DUAL = 100 kHz unless otherwise stated. SCLK CURRENT vs. TEMP REF V CURRENT vs. TEMP D V CURRENT vs. SCLK FREQ (SINGLE ...
Page 16
Typical Performance Characteristics MHz, DUAL = 100 kHz unless otherwise stated. SCLK CURRENT vs. SCLK (SINGLE D REF V CURRENT vs. SCLK (SINGLE D D CMRR vs. CM RIPPLE FREQ ...
Page 17
Functional Description The ADC122S706 is a dual 12-bit, simultaneous sampling Analog-to-Digital (A/D) converter. The converter is based on a successive-approximation register (SAR) architecture where the differential nature of the analog inputs is main- tained from the internal track-and-hold circuits throughout ...
Page 18
Single-Ended Input Operation For single-ended operation, the non-inverting inputs of the ADC122S706 can be driven with a signal that has a maximum to minimum value range that is equal to or less than twice the reference voltage. The inverting ...
Page 19
CS Input The CS (chip select bar active low input that is TTL and CMOS compatible. The ADC122S706 is in conversion mode when CS is low and power-down mode when CS is high result, CS ...
Page 20
Burst Mode Operation Normal operation of the ADC122S706 requires the SCLK fre- quency to be sixteen times the sample rate and the CS rate to be the same as the sample rate. However, in order to min- imize power ...
Page 21
APPLICATION CIRCUITS The following figures are examples of the ADC122S706 in typical application circuits. These circuits are basic and will generally require modification for specific circumstances. 6.1 Data Acquisition Figure 12 shows a basic low cost, low power data ...
Page 22
Bridge Sensor Application Figure 14 shows an example of interfacing the ADC122S706 to a pair of bridge sensors. The application assumes that the bridge sensors require buffering and amplification to fully uti- lize the dynamic range of the ADC ...
Page 23
Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead TSSOP Order Number ADC122S706CIMM NS Package Number MTC14 23 www.national.com ...
Page 24
... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock Conditioners www.national.com/timing Data Converters www.national.com/adc Displays www.national.com/displays Ethernet www.national.com/ethernet Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www ...