MPC8358 FREESCALE [Freescale Semiconductor, Inc], MPC8358 Datasheet
MPC8358
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MPC8358 Summary of contents
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... Freescale Semiconductor Technical Data MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications This document provides an overview of the MPC8358E ™ PowerQUICC II Pro processor revision 2.1 PBGA features, including a block diagram showing the major functional components. This device is a cost-effective, highly integrated communications processor that addresses the needs of the networking, wireless infrastructure and telecommunications markets ...
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... ATM, Ethernet, HDLC, and POS. The QUICC Engine module's enhanced interworking eases the transition and reduces investment costs from ATM to IP based systems. The MPC8358E has a single DDR SDRAM memory controller. The MPC8358E also offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine. ...
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... Serial DMA channel for receive and transmit on all serial channels — QE peripheral request interface (for SEC, PCI, IEEE® Std 1588™) — Six UCCs on the MPC8358E supporting the following protocols and interfaces (not all of them simultaneously): – IEEE Std. 1588 protocol supported – ...
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... One UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY — Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management — Four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3 rates in clear channel — Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC serial channels — ...
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... DDR SDRAM memory controller on the MPC8358E — Programmable timing supporting both DDR1 and DDR2 SDRAM — On the MPC8358E, the DDR bus can be configured as a 32-bit or a 64-bit bus — 32- or 64-bit data interface 266 MHz (for the MPC8358E) data rate — ...
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... External and internal interrupts directed to communication processor — Redirects interrupts to external INTA pin when in core disable mode — Unique vector number for each interrupt source • Dual industry-standard I — Two-wire interface MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev interfaces Freescale Semiconductor ...
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... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8358E. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. ...
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... REF the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation shown in Figure 3. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Table 1. Absolute Maximum Ratings Symbol Core supply voltage V DD PLL supply voltage ...
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... and negative direction. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Symbol Core supply voltage PLL supply voltage DDR DDR2 2 C, SPI, must track each other and must vary in the same direction—either in the positive or ...
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... PCI interface of the device for the 3.3-V signals, respectively. Overvoltage Waveform Undervoltage Waveform Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Not to Exceed 10 interface refers to the clock period associated with the bus clock interface. ...
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... I/O pins and to eliminate excessive current draw, apply the core voltage (V ) before the I/O voltage (GV DD MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Table 3. Output Drive Capability Output Impedance (Ω) 36 (half strength mode) ...
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... I/O voltage supplies ( another. 2.2.2 Power-Down Sequencing The MPC8358E does not require the core supply voltage and I/O supply voltages to be powered-down in any particular order. 3 Power Characteristics The estimated typical power dissipation values are shown in Table 4. MPC8358E PBGA Core Power Dissipation Core CSB ...
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... Ethernet I/O GMII or TBI Load = 20 pf RGMII or RTBI Other I/O 4 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8358E. 4.1 DC Electrical Characteristics Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device. Table 6. CLKIN DC Electrical Characteristics Parameter ...
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... DC electrical characteristics for the RESET pins of the device. Table 8. RESET Pins DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Table 7. CLKIN AC Timing Specifications Symbol Min f — CLKIN ...
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... Input hold time for POR config signals with respect to negation of HRESET Time for the device to turn off POR config signals with respect to the assertion of HRESET MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Symbol Condition Min ...
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... QE I/O frequencies and the minimal QE core frequency for each interface. Table 11. QE Operating Frequency Limitations Interface Ethernet Management: MDC/MDIO MII RMII GMII/RGMII/TBI/RTBI MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Table 10. PLL and DLL Lock Times Min — 7680 Section 22, “Clocking,” ...
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... I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (V = 1.420 V) OUT MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Interface Operating Max interface Frequency (MHz) Bit Rate (Mbps) 10 (max) 10 ...
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... Input high voltage Input low voltage Output leakage current Output high current (V = 1.95 V) OUT Output low current (V = 0.35 V) OUT MV input leakage current REF MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev 13 — VREF I — all times. ...
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... AC timing specifications for the DDR SDRAM interface when GV (typ Table 17. DDR SDRAM Input AC Timing Specifications Mode for GV At recommended operating conditions with GV Parameter AC input low voltage MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor I — all times and to track GV DC variations as measured at the receiver ...
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... ADDR/CMD output setup with respect to MCK ADDR/CMD output hold with respect to MCK MCS(n) output setup with respect to MCK MCS(n) output hold with respect to MCK MCK to MDQS MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev 2.5 V ± 5 ...
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... All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that t conventions described in note timing values are based on the DDR data rate, which is twice the DDR memory bus frequency. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor (continued) ...
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... AC test load for the DDR bus. Output Table 20. DDR and DDR2 SDRAM Measurement Conditions Symbol OUT Notes: 1. Data input threshold measurement point. 2. Data output measurement point. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev MCK[n] MCK[n] t MCK t AOSKEW(max) CMD t AOSKEW(min) ...
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... If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM. Table 21. Expected Delays for Address/Command 4 devices (12 pF) 9 devices (27 pF) 36 devices (108 pF compensation capacitor 36 devices (108 pF compensation capacitor MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor t MCK t ,t DDKHAS ...
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... Subsequent bit values are sampled each 16 8 UCC Ethernet Controller: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Symbol Min V 2 ...
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... Output high voltage Output low voltage Input high voltage Input low voltage Input current MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management Section 8.3, “Ethernet Management Interface Electrical Table 25. The potential applied to the input of a GMII, MII, RMII, TBI, into a RGMII receiver powered from a 2 ...
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... This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming convention. Figure 8 shows the GMII transmit AC timing diagram. GTX_CLK TXD[7:0] TX_EN TX_ER MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev 3.3 V ± 10 Symbol t ...
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... R (rise (fall). Figure 9 shows the GMII receive AC timing diagram. RX_CLK RXD[7:0] RX_DV RX_ER MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management / OV of 3.3 V ± 10 ...
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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 10 shows the MII transmit AC timing diagram. TX_CLK TXD[3:0] TX_EN TX_ER MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev 3.3 V ± 10 ...
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... AC test load. Output Figure 12 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management / OV of 3.3 V ± 10 Symbol ...
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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 13 shows the RMII transmit AC timing diagram. REF_CLK TXD[1:0] TX_EN Figure 13. RMII Transmit AC Timing Diagram MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev 3.3 V ± 10 ...
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... AC test load. Output Figure 15 shows the RMII receive AC timing diagram. REF_CLK RXD[1:0] CRS_DV RX_ER MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management / OV of 3.3 V ± 10 Symbol ...
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... This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention. Figure 16 shows the TBI transmit AC timing diagram. GTX_CLK TXD[7:0] TX_EN TX_ER MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev 3.3 V ± 10 ...
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... RCG are measured from riding edge of PMA_RX_CLK0. Figure 17 shows the TBI receive AC timing diagram. PMA_RX_CLK1 RCG[9:0] PMA_RX_CLK0 MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management / OV of 3.3 V ± 10%. DD ...
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... SKRGTKHDX maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2 option 2. Please refer to QE_ENET10 in the device errata document. UCC1 does meet t MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Specifications of 2.5 V ± 5%. ...
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... Table 35. MII Management DC Electrical Characteristics when powered at 3.3V Parameter Symbol Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management t t SKRGTKHDX TXD[8:5] ...
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... MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz). 3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay and for a ce_clk of 300 MHz, the delay is 63 ns). MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev — ...
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... These are asynchronous signals. 3. Inputs need to be stable at least one TMR clock. 9 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8358E. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor t MDC t t ...
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... Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Symbol Min ...
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... LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to output valid MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Symbol t ...
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... DLL bypass mode is not recommended for use at frequencies above 66MHz. Figure 20 provides the AC test load for the local bus. Output MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Symbol t ...
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... Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 21. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor t LBIVKH t t LBKHOX LBKHOV t LBKHOZ ...
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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev LBIVKH t LBKHOV t LBKHOZ ...
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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor t LBKHOZ t LBKHOV t ...
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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev LBKHOZ t LBKHOV t LBIVKH ...
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... DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the device. Table 41. JTAG interface DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t ...
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... TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design and characterization. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Table 2). ...
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... JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor = 50 Ω JTKHKL t JTG VM = Midpoint Voltage (OV DD /2) ...
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... JTKLOX TDO TDO Output Data Valid Figure 31. Test Access Port Timing Diagram This section describes the DC and AC electrical characteristics for the I MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev JTIVKH Input Data Valid t JTKLOV ...
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... Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: CBUS compatible masters Rise time of both SDA and SCL signals MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor 2 C interface of the device. 2 Table 43 Electrical Characteristics of 3.3 V ± ...
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... AC test load for the I Output Figure 33 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Electrical Specifications (continued) Table 43). 1 Symbol t I2CF t I2PVKH t I2KHDX ...
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... PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8358E. 12.1 PCI DC Electrical Characteristics Table 45 provides the DC electrical characteristics for the PCI interface of the device. Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage ...
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... Input timings are measured at the pin. Figure 34 provides the AC test load for PCI. Output Figure 35 shows the PCI input AC timing conditions. CLK Input Figure 35. PCI Input AC Timing Measurement Conditions MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Symbol t PCKHOV t PCKHOX t ...
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... Output Delay High-Impedance Output Figure 36. PCI Output AC Timing Measurement Condition 13 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8358E. 13.1 Timers DC Electrical Characteristics Table 48 provides the DC electrical characteristics for the device timer pins, including TIN, TOUT, TGATE and RTC_CLK. ...
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... Timers inputs are required to be valid for at least t operation. Figure 37 provides the AC test load for the timers. Output 14 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8358E. 14.1 GPIO DC Electrical Characteristics Table 50 provides the DC electrical characteristics for the device GPIO. Table 50. GPIO DC Electrical Characteristics ...
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... Output low voltage Output low voltage Notes: 1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT, and CE ports Interrupts. 2. IRQ_OUT and MCP_OUT are open drain pins, thus V MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor = 50 Ω Figure 38. GPIO AC Test Load Table 52 ...
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... IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least t 16 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8358E. 16.1 SPI DC Electrical Characteristics Table 54 provides the DC electrical characteristics for the device SPI ...
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... SPIMOSI (See Note) Output Signals: SPIMISO (See Note) Note: The clock edge is selectable on SPI. Figure 40. SPI AC Timing in Slave mode (External Clock) Diagram MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Table 55. SPI AC Timing Specifications Symbol t NEIVKH t ...
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... TDM/SI input and output AC timing specifications. Table 57. TDM/SI AC Timing Specifications Characteristic TDM/SI outputs—External clock delay TDM/SI outputs—External clock high impedance TDM/SI inputs—External clock input setup time MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev NIIXKH t NIIVKH ...
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... TDM/SI (See Note) Output Signals: TDM/SI (See Note) Note: The clock edge is selectable on TDM/SI Figure 43. TDM/SI AC Timing (External Clock) Diagram MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor 1 2 Symbol t SEIXKH (first two letters of functional block)(signal)(state) TDM/ Ω ...
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... UTOPIA/POS 18 UTOPIA/POS This section describes the DC and AC electrical specifications for the UTOPIA/POS of the MPC8358E. 18.1 UTOPIA/POS DC Electrical Characteristics Table 58 provides the DC electrical characteristics for the device UTOPIA. Table 58. UTOPIA DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current 18 ...
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... This section describes the DC and AC electrical specifications for the high level data link control (HDLC), BiSync, transparent, and synchronous UART protocols of the MPC8358E. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART = 50 Ω ...
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... HIKHOX state (H) until outputs (O) are invalid (X). MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Symbol Condition Min – ...
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... AC timing from specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART ...
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... Serial CLK (output) Input Signals: (See Note) Output Signals: (See Note) Note: The clock edge is selectable. Figure 49. AC Timing (Internal Clock) Diagram MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev HEIXKH t HEKHOV t HEKHOX ...
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... USB This section provides the AC and DC electrical specifications for the USB interface of the MPC8358E. 20.1 USB DC Electrical Characteristics Table 63 provides the DC electrical characteristics for the USB interface. Parameter High-level input voltage Low-level input voltage High-level output voltage, = –100 μ Low-level output voltage, = 100 μ ...
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... Figure 50 provide the AC test load for the USB. Output 21 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8358E is available in a plastic ball grid array (PBGA), see Section 21.2, “Mechanical Dimensions of the PBGA 21.1 Package Parameters for the PBGA Package The package parameters for rev 2 ...
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... Figure 51. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Package and Pin Listings 67 ...
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... PCI_RESET_OUT/ PF[6] PCI_AD[0:31]/ PG[0:31] PCI_C_BE[0:3]/ PF[7:10] MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Table 65. MPC8358E PBGA Pinout Listing Package Pin Number DDR SDRAM Memory Controller Interface AD20, AG24, AF24, AH24, AF23, AE22, AH26, AD21, AH25, AD22, AF27, AB24, AG25, AC22, AE25, AC24, ...
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... M66EN/ CE_PF[4] LAD[0:31] LDP[0:3] LA[27:31] LCS[0:5] LWE[0:3] LBCTL LALE LGPL0/ LSDA10/ cfg_reset_source0 LGPL1/ LSDWE/ cfg_reset_source1 MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number AA4 W4 W5 AB3 AB1 AA2 U6 AC1 W6 R2, T4, U1 T3, R5, T1 AE5 AH3 ...
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... IRQ[3]/ CORE_SRESET IRQ[4:5] IRQ[6:7] UART1_SOUT UART1_SIN UART1_CTS UART1_RTS IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL CE_PA[0] MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Package Pin Number AH19 AE18 AG19 AF19 AD8 AC9 AG6 AE7 AG4 AC8 Programmable Interrupt Controller ...
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... CE_PC[10:30] CE_PD[0:27] CE_PE[0:31] CE_PF[0:3] PCI_CLK[0]/ PF[26] PCI_CLK[1:2]/ PF[27:28] CLKIN PCI_SYNC_IN PCI_SYNC_OUT/ PF[29] TCK MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number A22, C20 C3, D3, C2, D2, B1 F18 E3, C1, B2, D1 B21, D19 E4 E18 M2, N5, N3, N4, N2 F17 N1, P1, P2, P4 ...
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... SRESET THERM0 THERM1 GND MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Package Pin Number AE8 AG7 AH7 AG8 Test AF9 AE27 PMC AF4 System Control AE9 AG9 AH10 Thermal Management ...
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... Pins" for information about the two UCC2 Ethernet interface options. 11 recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω resistor for DDR2. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number ...
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... CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev e300 core ...
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... DDRC1 memory bus clock outputs (MEMC1_MCK and MEMC1_MCK). However, the data rate is the same frequency as ddr1_clk. The internal lb_clk frequency is determined by the following equation: lb_clk = csb_clk × RCWL[LBCM]) MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Clocking 75 ...
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... The DDR data rate is 2x the DDR memory bus frequency. 3 The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCCR[CLKDIV]) which is in turn the csb_clk frequency (depending on RCWL[LBCM]). MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Table 66 specifies which units have a configurable clock Table 66 ...
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... The VCO divider must be set properly so that the system VCO frequency is in the range of 600-1400 MHz. The system VCO frequency is derived from the following equations: csb_clk = {PCI_SYNC_IN × CFG_CLKIN_DIV)} × SPMF MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Table 68. System PLL Multiplication Factors System PLL Multiplication ...
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... Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Table 70. CSB Frequency Options csb_clk : SPMF Input Clock 16.67 2 Ratio 0010 0011 0100 ...
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... RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 71 in Table 71 should be considered reserved. RCWL[COREPLL] 0-1 2-5 nn 0000 00 0001 01 0001 MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor csb_clk : SPMF Input Clock 16.67 2 Ratio 0010 0011 0100 0101 ...
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... MHz. Having a core frequency below the CSB frequency is not a possible option because the core frequency must be equal to or greater than the CSB frequency. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev core_clk : csb_clk Ratio ...
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... MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor QUICC Engine PLL Multiplication RCWL[CEPDF] Factor = RCWL[CEPMF] / (1+RCWL[CEPDF]) 0 × Reserved 0 × × × ...
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... Notes 1. Reserved modes are not listed. The RCWL[CEVCOD] denotes the QE PLL VCO internal frequency as shown in RCWL[CEVCOD] MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev QUICC Engine PLL Multiplication RCWL[CEPDF] Factor = RCWL[CEPMF] / (1+RCWL[CEPDF ...
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... MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor NOTE “Clocking,” for the appropriate operating frequencies for your Table 74. Suggested PLL Configurations Input CSB Freq Core Freq CEPDF ...
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... Choose the up or down sections in the table according to input clock rate 33 MHz or 66 MHz. 2. Select a suitable CSB and core clock rates from configuration bits. 3. Select a suitable QUICC Engine clock rate from configuration bits. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Input CSB Freq Core Freq ...
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... Junction-to-ambient Natural Convection on four layer board (2s2p) Junction-to-ambient (@1 m/s) on single layer board (1s) Junction-to-ambient (@ 1 m/s) on four layer board (2s2p) Junction-to-board thermal Junction-to-case thermal MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Input Clock CSB Freq Core Freq ...
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... The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev ...
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... When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance θ JA where: MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor × θ JB ...
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... More detailed thermal models can be made available on request. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev For instance, the user can change the size of the heat θ ...
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... Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor 603-224-9988 408-749-7601 818-842-7277 408-436-8770 800-522-6752 603-635-5102 781-935-4850 800-248-2481 ...
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... System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8358E. Additional information can be found in AN3097, MPC8360E/MPC8358E PowerQUICC™ Design Checklist, Rev. 1. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev 800-347-4572 × P ...
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... Therefore recommended that the system designer place at least one decoupling capacitor at each V decoupling capacitors should receive their power from separate V MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor 1) generates the platform clock from the externally supplied CLKIN Section 22.1, “ ...
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... When data is held high, SW1 is closed (SW2 is open) and R OV /2. R then becomes the resistance of the pull-up devices other in value. Then MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev and LV planes, to enable quick recharging of the smaller chip ...
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... These pins are generally used as output only pins in normal operation. While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor OV ...
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... Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number. MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Table 78. Document Revision History ...
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... Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies. Table 80 shows the SVR settings by device and package type. MPC8358E MPC8358 MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1 Freescale Semiconductor Table 79. Part Numbering Nomenclature ...
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... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8358EEC Rev. 1 12/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...