pca9512a NXP Semiconductors, pca9512a Datasheet

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pca9512a

Manufacturer Part Number
pca9512a
Description
Pca9512a Level Shifting Hot Swappable I2c-bus And Smbus Bus Buffer
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
The PCA9512A is a hot swappable I
insertion into a live backplane without corruption of the data and clock buses and includes
two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems
while maintaining the best noise margin for each voltage level. Either pin may be powered
with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply
voltage is higher. Control circuitry prevents the backplane from being connected to the
card until a stop bit or bus idle occurs on the backplane without bus contention on the
card. When the connection is made, the PCA9512A provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
The PCA9512A rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9512A incorporates a digital
input pin that enables and disables the rise time accelerators on all four SDAn and SCLn
pins.
During insertion, the PCA9512A SDAn and SCLn pins are precharged to 1 V to minimize
the current required to charge the parasitic capacitance of the chip.
The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to
be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and
to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot connect to the
static offset I/Os used on the PCA9515/15A/16/16A/18, PCA9517 B side, or
P82B96 Sx/y side.
PCA9512A
Level shifting hot swappable I
Rev. 01 — 7 October 2005
Bidirectional buffer for SDA and SCL lines increases fanout and prevents SDA and
SCL corruption during live board insertion and removal from multi-point backplane
systems
Compatible with I
Built-in V/ t rise time accelerators on all SDAn and SCLn pins (0.6 V threshold) with
ability to disable V/ t rise time accelerator through the ACC pin for lightly loaded
systems
5 V to 3.3 V level translation with optimum noise margin
High-impedance SDAn and SCLn pins for V
1 V precharge on all SDAn and SCLn pins
Supports clock stretching and multiple master arbitration and synchronization
Operating power supply voltage range: 2.7 V to 5.5 V
I/Os are not 5.5 V tolerant
0 Hz to 400 kHz clock frequency
2
C-bus Standard mode, I
2
C-bus and SMBus buffer that allows I/O card
2
2
C-bus and SMBus bus buffer
C-bus Fast mode, and SMBus standards
CC
or V
CC2
= 0 V
Product data sheet

Related parts for pca9512a

pca9512a Summary of contents

Page 1

... SDAn and SCLn pins. During insertion, the PCA9512A SDAn and SCLn pins are precharged minimize the current required to charge the parasitic capacitance of the chip. The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and to the A side of the PCA9517 ...

Page 2

... PCA9512AD PA9512A SO8 PCA9512ADP 9512A TSSOP8 [1] Also known as MSOP8. Standard packing quantities and other packaging data are available at the Philips website. PCA9512A_1 Product data sheet Level shifting hot swappable I PCA9510A PCA9511A PCA9512A PCA9513A PCA9514A yes yes = 0 V yes yes CC - yes - - - ...

Page 3

... RCH1 100 k RCH2 SLEW RATE ACC DETECTOR SCLIN CONNECT 0.55V / CC 0.45V CC 100 s UVLO DELAY Fig 1. Block diagram of PCA9512A PCA9512A_1 Product data sheet Level shifting hot swappable SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION CONNECT 100 k RCH3 1 VOLT PRECHARGE 100 k RCH4 ...

Page 4

... Refer to 8.1 Start-up When the PCA9512A is powered up, either V more positive or they may be equal, however the PCA9512A will not leave the undervoltage lock out or initialization state until both V 2 either V state. In the undervoltage lock out state the connection circuitry is disabled, the rise time accelerators are disabled, and the precharge circuitry is also disabled ...

Page 5

... CC forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the PCA9512A. The same is also true for the SCLn pins. Noise between 0.7V the SDAIN and SCLIN pins, and 0.7V generally ignored because a falling edge is only recognized when it falls below 0.7V SDAIN and SCLIN (or 0 ...

Page 6

... Philips Semiconductors The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise time accelerator can be turned off) are a little different with the rise time accelerator turned off because the rise time accelerator will not pull the node up, but the same logic that turns on the accelerator turns the pull-down off ...

Page 7

... Rise time accelerators During positive bus transactions current source is switched on to quickly slew the SDA and SCL lines HIGH once the input level of 0.6 V for the PCA9512A is exceeded. The rising edge rate should be at least 1. guarantee turn on of the accelerators. ...

Page 8

... Placing a bus buffer on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the PCA9512A drives the capacitance of everything on the card and the backplane must drive only the capacitance of the bus buffer, which is less than 10 pF, the connector, trace, and all additional cards on the backplane. See Application Note AN10160, ‘ ...

Page 9

... SCL Remark: Application assumes bus capacitance within ‘proper operation’ region of Fig 7. Hot swapping multiple I/O cards into a backplane using the PCA9512A in a cPCI, VME, and AdvancedTCA system PCA9512A_1 Product data sheet Level shifting hot swappable I I/O PERIPHERAL CARD 1 POWER SUPPLY ...

Page 10

... CC SDA SCL Remark: Application assumes bus capacitance within ‘proper operation’ region of Fig 8. Hot swapping multiple I/O cards into a backplane using the PCA9512A with a custom connector SDA SCL Remark: Application assumes bus capacitance within ‘proper operation’ region of Fig 9 ...

Page 11

... Level shifting hot swappable 0. CC2 SDAIN SDAOUT SCLIN SCLOUT PCA9512A ACC GND Conditions 10 s maximum Rev. 01 — 7 October 2005 PCA9512A 2 C-bus and SMBus bus buffer CARD_V ( CARD_SDA CARD_SCL 002aab794 Min Max 0.5 +7 0.5 +7 0.5 +7 ...

Page 12

... 3 CC2 digital; guaranteed by design, not subject to test = 0 V; SDAn, SCLn pins mA 2.7 V; sink 2.7 V CC2 SDAn, SCLn pins 5 5 CC2 Rev. 01 — 7 October 2005 PCA9512A 2 C-bus and SMBus bus buffer Min Typ Max [1] 2.7 - 5.5 [1] 2.7 - 5.5 - 1.8 3.6 - 1.7 2.9 [1] 0.8 1.1 1.2 [3] - ...

Page 13

... PCA9512A_1 Product data sheet Level shifting hot swappable I Conditions and V 2 when idle or stop time begins. CC CC2 voltage, as shown in Section 11.1 “Typical performance CC Section 11.1 “Typical performance Rev. 01 — 7 October 2005 PCA9512A 2 C-bus and SMBus bus buffer Min Typ Max [ 400 [7] 1 [7] ...

Page 14

... Level shifting hot swappable I 002aab795 I trt(pu) (mA) + amb Fig 12. I 002aab589 V O (mV) + amb = 10 k PU(out) Fig 14. Connection circuitry V Rev. 01 — 7 October 2005 PCA9512A 2 C-bus and SMBus bus buffer +25 T amb versus temperature trt(pu) 350 V I 250 150 ...

Page 15

... Product data sheet Level shifting hot swappable PULSE D.U.T. GENERATOR the pulse generator o Rev. 01 — 7 October 2005 PCA9512A 2 C-bus and SMBus bus buffer 100 pF 002aab595 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...

Page 16

... 0.49 0.25 5.0 4.0 1.27 0.36 0.19 4.8 3.8 0.019 0.0100 0.20 0.16 0.244 0.05 0.014 0.0075 0.19 0.15 0.228 REFERENCES JEDEC JEITA MS-012 Rev. 01 — 7 October 2005 PCA9512A 2 C-bus and SMBus bus buffer detail 6.2 1.0 0.7 1.05 0.25 0.25 5.8 0.4 0.6 0.039 ...

Page 17

... 2.5 scale (1) ( 0.45 0.28 3.1 3.1 0.65 0.25 0.15 2.9 2.9 REFERENCES JEDEC JEITA Rev. 01 — 7 October 2005 PCA9512A 2 C-bus and SMBus bus buffer detail 5.1 0.7 0.94 0.1 0.1 0.1 4.7 0.4 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...

Page 18

... PCA9512A_1 Product data sheet Level shifting hot swappable I 2 called small/thin packages. Rev. 01 — 7 October 2005 PCA9512A 2 C-bus and SMBus bus buffer 3 350 mm so called © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...

Page 19

... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 01 — 7 October 2005 PCA9512A 2 C-bus and SMBus bus buffer Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable ...

Page 20

... Peripheral Component Interface PCI Industrial Computer Manufacturers Group System Management Bus VERSAModule Eurocard Data sheet status Change notice Product data sheet - Rev. 01 — 7 October 2005 PCA9512A 2 C-bus and SMBus bus buffer Doc. number Supersedes - - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...

Page 21

... Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of Koninklijke Philips Electronics N.V. Rev. 01 — 7 October 2005 PCA9512A 2 C-bus and SMBus bus buffer © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...

Page 22

... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands PCA9512A 2 C-bus and SMBus bus buffer Date of release: 7 October 2005 Document number: PCA9512A_1 ...

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