ATTINY261-20MU Atmel, ATTINY261-20MU Datasheet - Page 48

• Manufacturer Part Number: ATTINY261-20MU
• Description: IC MCU AVR 2K FLASH 20MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: 2-Wire, SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

48
ATtiny261/461/861
the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after
each interrupt.
Table 8-2.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. This bit must also be set when
changing the prescaler bits.
Watchdog Timer” on page 45.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above.
Timer” on page 45.
In safety level 1, WDE is overridden by WDRF in MCUSR. See
ter” on page 47
To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure
described above. This feature ensures multiple resets during conditions causing failure, and a
safe start-up after the failure.
Note:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
WDE
0
0
1
1
ten to WDE even though it is set to one before the disable operation starts.
If the watchdog timer is not going to be used in the application, it is important to go through a
watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally
enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which
in turn will lead to a new watchdog reset. To avoid this situation, the application software should
always clear the WDRF flag and the WDE control bit in the initialization routine.
Watchdog Timer Configuration
for description of WDRF. This means that WDE is always set when WDRF is set.
WDIE
0
1
0
1
See “Timed Sequences for Changing the Configuration of the Watchdog
Watchdog Timer State
Stopped
Running
Running
Running
See “Timed Sequences for Changing the Configuration of the
Action on Time-out
None
Interrupt
Reset
Interrupt
“MCUSR – MCU Status Regis-
2588E–AVR–08/10