PIC18LF24J11-I/SS Microchip Technology, PIC18LF24J11-I/SS Datasheet - Page 521

• Manufacturer Part Number: PIC18LF24J11-I/SS
• Description: IC PIC MCU FLASH 16K 2V 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF24J11-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 31 KHz
• Number Of Programmable I/os: 16
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RTCEN Bit Write .............................................................. 233
S
SCKx ................................................................................ 266
SDIx ................................................................................. 266
SDOx ............................................................................... 266
SEC_IDLE Mode ................................................................ 46
SEC_RUN Mode ................................................................ 42
Serial Clock, SCKx ........................................................... 266
Serial Data In (SDIx) ........................................................ 266
Serial Data Out (SDOx) ................................................... 266
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 441
Shoot-Through Current .................................................... 259
Slave Select (SSx) ........................................................... 266
SLEEP ............................................................................. 442
Software Simulator (MPLAB SIM) .................................... 458
Special Event Trigger. See Compare (ECCP Mode).
Special Features of the CPU ........................................... 389
SPI Mode (MSSP) ............................................................ 266
SSPOV ............................................................................. 310
SSPOV Status Flag ......................................................... 310
SSPxSTAT Register
SSx .................................................................................. 266
Stack Full/Underflow Resets .............................................. 75
SUBFSR .......................................................................... 453
SUBFWB .......................................................................... 442
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Peripheral Module Disable (PMD) Register ............. 238
Register Interface ..................................................... 233
Register Maps .......................................................... 239
Reset ........................................................................ 238
Value Registers (RTCVAL) ...................................... 227
Associated Registers ............................................... 275
Bus Mode Compatibility ........................................... 274
Clock Speed, Interactions ........................................ 274
Effects of a Reset ..................................................... 274
Enabling SPI I/O ...................................................... 270
Master Mode ............................................................ 271
Master/Slave Connection ......................................... 270
Operation ................................................................. 269
Operation in Power-Managed Modes ...................... 274
Registers .................................................................. 267
Serial Clock .............................................................. 266
Serial Data In ........................................................... 266
Serial Data Out ........................................................ 266
Slave Mode .............................................................. 272
Slave Select ............................................................. 266
Slave Select Synchronization .................................. 272
SPI Clock ................................................................. 271
SSPxBUF Register .................................................. 271
SSPxSR Register ..................................................... 271
Typical Connection .................................................. 270
R/W Bit ............................................................. 290, 293
ALRMVAL Register Mapping ........................... 236
Calibration ........................................................ 236
Clock Source ................................................... 234
Digit Carry Rules .............................................. 234
General Functionality ....................................... 235
Leap Year ........................................................ 235
Register Mapping ............................................. 235
RTCVAL Register Mapping ............................. 236
Safety Window for Register Reads and Writes 235
Write Lock ........................................................ 235
Device .............................................................. 238
Power-on Reset (POR) .................................... 238
Open-Drain Output Option ............................... 269
PIC18F46J11 FAMILY
SUBLW ............................................................................ 443
SUBULNK ........................................................................ 453
SUBWF ............................................................................ 443
SUBWFB ......................................................................... 444
SWAPF ............................................................................ 444
T
Table Pointer Operations with TBLRD, TBLWT (table) ... 100
Table Reads/Table Writes ................................................. 75
T
TBLRD ............................................................................. 445
TBLWT ............................................................................ 446
Timer0 ............................................................................. 191
Timer1 ............................................................................. 195
Timer2 ............................................................................. 207
Timer3 ............................................................................. 209
Timer4 ............................................................................. 219
Timing Diagrams
AD
Associated Registers ............................................... 193
Operation ................................................................. 192
Overflow Interrupt .................................................... 193
Prescaler ................................................................. 193
Prescaler Assignment (PSA Bit) .............................. 193
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 193
Reads and Writes in 16-Bit Mode ............................ 192
Source Edge Select (T0SE Bit) ............................... 192
Source Select (T0CS Bit) ........................................ 192
16-Bit Read/Write Mode .......................................... 200
Associated Registers ............................................... 206
Clock Source Selection ........................................... 198
Gate ......................................................................... 202
Interrupt ................................................................... 201
Operation ................................................................. 198
Oscillator .......................................................... 195, 200
Resetting, Using the ECCP Special Event Trigger .. 202
TMR1H Register ...................................................... 195
TMR1L Register ...................................................... 195
Use as a Clock Source ............................................ 201
Associated Registers ............................................... 208
Interrupt ................................................................... 208
Operation ................................................................. 207
Output ...................................................................... 208
16-Bit Read/Write Mode .......................................... 213
Associated Registers ............................................... 217
Gate ......................................................................... 213
Operation ................................................................. 212
Oscillator .......................................................... 209, 213
Overflow Interrupt ............................................ 209, 217
Special Event Trigger (ECCP) ................................. 217
TMR3H Register ...................................................... 209
TMR3L Register ...................................................... 209
Associated Registers ............................................... 220
Interrupt ................................................................... 220
MSSP Clock Shift .................................................... 220
Operation ................................................................. 219
Output ...................................................................... 220
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 219
Prescaler. See Prescaler, Timer4.
TMR4 Register ........................................................ 219
TMR4 to PR4 Match Interrupt .......................... 219, 220
A/D Conversion ....................................................... 497
Asynchronous Reception ......................................... 334
Asynchronous Transmission ................................... 332
.................................................................................. 351
Switching Assignment ..................................... 193
Layout Considerations ..................................... 201
DS39932C-page 521