PIC18LF24J11-I/SS Microchip Technology, PIC18LF24J11-I/SS Datasheet - Page 86

• Manufacturer Part Number: PIC18LF24J11-I/SS
• Description: IC PIC MCU FLASH 16K 2V 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF24J11-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 31 KHz
• Number Of Programmable I/os: 16
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F46J11 FAMILY
TABLE 5-4:
DS39932C-page 86
ALRMRPT
ALRMVALH
ALRMVALL
LATE
LATD
LATC
LATB
LATA
DMACON1
DMATXBUF
DMACON2
HLVDCON
PORTE
PORTD
PORTC
PORTB
PORTA
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
TMR3H
TMR3L
T3CON
TMR4
PR4
T4CON
SSP2BUF
SSP2ADD/
SSP2MSK
SSP2STAT
SSP2CON1
SSP2CON2
CMSTAT
PMADDRH/
PMDOUT1H
PMADDRL/
PMDOUT1L
PMDIN1H
PMDIN1L
TXADDRL
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
(5)
(5)
(4)
(5)
(5)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking Modes” for details.
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information.
Alarm Value Register Window High Byte, Based on ALRMPTR<1:0>
Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0>
SPI DMA Transmit Buffer
EUSART1 Baud Rate Generator Register High Byte
EUSART2 Baud Rate Generator Register High Byte
Timer3 Register High Byte
Timer3 Register Low Byte
Timer4 Register
Timer4 Period Register
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register (I
Parallel Port Out Data High Byte (Buffer 1)
Parallel Master Port Address Low Byte
Parallel Port Out Data Low Byte (Buffer 0)
Parallel Port In Data High Byte (Buffer 1)
Parallel Port In Data Low Byte (Buffer 0)
SPI DMA Transit Data Pointer Low Byte
VDIRMAG
TMR3CS1
DLYCYC3
SSCON1
ABDOVF
ABDOVF
ARPT7
LATD7
LATC7
LATB7
LATA7
WCOL
GCEN
GCEN
RDPU
MSK7
Bit 7
SMP
RD7
RC7
RB7
RA7
—
—
—
—
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED)
T4OUTPS3 T4OUTPS2 T4OUTPS1
TMR3CS0
DLYCYC2
ACKSTAT
ACKSTAT
SSCON0
BGVST
SSPOV
ARPT6
LATD6
LATC6
RCIDL
RCIDL
LATB6
LATA6
REPU
MSK6
Bit 6
RD6
RC6
CKE
RB6
RA6
CS1
—
—
Parallel Master Port Address High Byte
ADMSK5
2
DLYCYC1
T3CKPS1
C™ Slave mode), MSSP2 Baud Rate Reload Register (I
ACKDT
RXDTP
RXDTP
SSPEN
ARPT5
LATD5
LATC5
LATB5
LATA5
TXINC
IRVST
MSK5
Bit 5
RD5
RC5
RB5
RA5
D/A
—
—
—
(4)
ADMSK4
DLYCYC0
T3CKPS0
HLVDEN
ACKEN
ARPT4
TXCKP
TXCKP
LATD4
LATC4
RXINC
LATB4
MSK4
Bit 4
RD4
RC4
CKP
RB4
—
—
—
—
—
P
(4)
T4OUTPS0
ADMSK3
DUPLEX1
INTLVL3
HLVDL3
SSPM3
ARPT3
BRG16
BRG16
LATD3
LATC3
LATB3
LATA3
MSK3
RCEN
Bit 3
RD3
RC4
RB3
RA3
—
—
—
—
S
(4)
ADMSK2
DUPLEX0
TMR4ON
T3SYNC
INTLVL2
HLVDL2
SSPM2
ARPT2
LATD2
LATC2
LATE2
LATB2
LATA2
MSK2
Bit 2
RD2
RC2
PEN
RE2
RB2
RA2
R/W
—
—
—
(4)
2
C™ Slave mode. See Section 18.5.3.2 “Address
2
ADMSK1
DLYINTEN
T4CKPS1
C Master mode)
INTLVL1
HLVDL1
SSPM1
COUT2
ARPT1
LATE1
LATD1
LATC1
LATB1
LATA1
MSK1
RSEN
RD16
WUE
WUE
Bit 1
RE1
RD1
RC1
RB1
RA1
UA
© 2009 Microchip Technology Inc.
(4)
T4CKPS0 -000 0000 67, 219
TMR3ON
INTLVL0
HLVDL0
DMAEN
ABDEN
ABDEN
SSPM0
COUT1
ARPT0
LATE0
LATD0
LATC0
LATB0
LATA0
MSK0
Bit 0
RE0
RD0
RC0
RB0
RA0
SEN
SEN
BF
xxx- xxxx
0000 0000 66, 226
xxxx xxxx
xxxx xxxx
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- xxxx
0000 0000 66, 278
xxxx xxxx
0000 0000 66, 279
0000 0000
00-- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0100 0-00 66, 324
0000 0000
0100 0-00 66, 324
xxxx xxxx
xxxx xxxx
0000 -000 67, 209
0000 0000
1111 1111
xxxx xxxx
0000 0000 67, 289
0000 0000 67, 289
1111 1111 67, 267
0000 0000 67, 287
0000 0000 67, 288
---- --11 67, 357
-000 0000 67, 173
0000 0000 67, 173
0000 0000 67, 173
0000 0000 67, 173
0000 0000
0000 0000
xxxx xxxx
POR, BOR
Value on
Details
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