PIC18LF24J11-I/SS Microchip Technology, PIC18LF24J11-I/SS Datasheet - Page 85

• Manufacturer Part Number: PIC18LF24J11-I/SS
• Description: IC PIC MCU FLASH 16K 2V 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF24J11-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 31 KHz
• Number Of Programmable I/os: 16
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 5-4:
© 2009 Microchip Technology Inc.
PSTR2CON
ECCP2AS
ECCP2DEL
CCPR2H
CCPR2L
CCP2CON
CTMUCONH
CTMUCONL
CTMUICON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
SPBRG2
RCREG2
TXREG2
TXSTA2
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
RCSTA2
OSCTUNE
T1GCON
RTCVALH
RTCVALL
T3GCON
TRISE
TRISD
TRISC
TRISB
TRISA
ALRMCFG
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking Modes” for details.
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information.
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
EUSART1 Baud Rate Generator Register Low Byte
EUSART1 Receive Register
EUSART1 Transmit Register
EUSART2 Receive Register
EUSART2 Transmit Register
Program Memory Control Register 2 (not a physical register)
RTCC Value Register Window High Byte, Based on RTCPTR<1:0>
RTCC Value Register Window Low Byte, Based on RTCPTR<1:0>
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0
EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL
CTMUEN
PMPIP
PMPIE
TMR1GE
TMR3GE
ALRMEN
P2RSEN
PMPIF
OSCFIP
OSCFIF
OSCFIE
INTSRC
SSP2IE
TRISD7
TRISC7
TRISB7
TRISA7
SSP2IP
SSP2IF
CMPL1
ITRIM5
CSRC
CSRC
SPEN
SPEN
P2M1
Bit 7
—
—
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED)
(5)
(5)
(5)
T1GPOL
T3GPOL
TRISD6
TRISC6
TRISB6
TRISA6
CMPL0
BCL2IP
BCL2IF
BCL2IE
P2DC6
ITRIM4
PLLEN
CHIME
CM2IP
CM2IF
CM2IE
P2M0
ADIP
ADIF
ADIE
Bit 6
RX9
RX9
TX9
TX9
—
—
—
CTMUSIDL
WPROG
AMASK3
TRISD5
TRISC5
T1GTM
T3GTM
TRISB5
TRISA5
P2DC5
DC2B1
ITRIM3
EUSART2 Baud Rate Generator Register Low Byte
CM1IP
CM1IF
CM1IE
RC2IP
RC2IF
RC2IE
RC1IP
RC1IF
RC1IE
TXEN
SREN
TXEN
SREN
TUN5
Bit 5
—
—
STRSYNC
T1GSPM
T3GSPM
AMASK2
TRISD4
TRISC4
TRISB4
P2DC4
DC2B0
ITRIM2
SYNC
CREN
SYNC
CREN
TGEN
FREE
TX2IP
TX2IF
TX2IE
TX1IP
TX1IF
TX1IE
TUN4
Bit 4
—
—
—
—
—
EDG1SEL1
PSS2AC1
CCP2M3
T1DONE
T3DONE
AMASK1
WRERR
TMR4IP
TMR4IE
T1GGO/
T3GGO/
EDGEN
TMR4IF
TRISD3
TRISC3
SENDB
ADDEN
SENDB
BCL1IP
BCL1IF
BCL1IE
SSP1IP
SSP1IF
SSP1IE
ADDEN
TRISB3
TRISA3
P2DC3
ITRIM1
STRD
TUN3
Bit 3
—
PIC18F46J11 FAMILY
EDGSEQEN
EDG1SEL0
PSS2AC0
CCP2M2
AMASK0
CTMUIP
CTMUIF
CTMUIE
T1GVAL
T3GVAL
CCP1IP
CCP1IF
CCP1IE
TRISE2
TRISD2
TRISC2
TRISB2
TRISA2
P2DC2
ITRIM0
WREN
BRGH
BRGH
LVDIP
LVDIE
STRC
FERR
LVDIF
FERR
TUN2
Bit 2
2
C™ Slave mode. See Section 18.5.3.2 “Address
ALRMPTR1 ALRMPTR0 0000 0000 66, 225
EDG2STAT EDG1STAT 0000 0000
PSS2BD1
TMR3GIP
TMR3GIE
TMR3GIF
CCP2M1
IDISSEN
T1GSS1
T3GSS1
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
P2DC1
IRNG1
OERR
OERR
TRMT
TRMT
STRB
TUN1
Bit 1
WR
PSS2BD0 0000 0000
CCP2M0
T1GSS0
T3GSS0
RTCCIP
RTCCIF
RTCCIE
CCP2IP
CCP2IE
TMR1IP
TMR1IF
TMR1IE
CCP2IF
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
P2DC0
IRNG0
STRA
RX9D
RX9D
TUN0
TX9D
TX9D
Bit 0
—
—
DS39932C-page 85
00-0 0001 65, 261
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0-00 000-
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0010 65, 322
0000 000x 65, 323
0000 0000
0000 0000
0000 0000
0000 0010 65, 322
---- ----
--00 x00- 65, 99
1111 1111 65, 122
0000 0000 65, 116
0000 0000 65, 119
111- 1111 65, 121
000- 0000 65, 115
000- 0000 65, 118
1111 1111 65, 120
0000 0000 65, 114
0000 0000 65, 117
0000 000x 66, 323
0000 0000 66, 36
0000 0x00 66, 196
0xxx xxxx
0xxx xxxx
0000 0x00 66, 210
---- -111
1111 1111
1111 1111
1111 1111
111- 1111
POR, BOR
Value on
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