DSPIC33FJ12MC201-I/SO Microchip Technology, DSPIC33FJ12MC201-I/SO Datasheet - Page 35

• Manufacturer Part Number: DSPIC33FJ12MC201-I/SO
• Description: IC DSPIC MCU/DSP 12K 20SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC201-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 12KB (12K x 8)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 15
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 15
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-1:
TABLE 4-2:
TABLE 4-3:
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
XMODSRT
XMODEND
YMODSRT
YMODEND
XBREV
DISICNT
Legend:
SFR Name
Name
Name
SFR
SFR
Addr
00C2
0060
0062
0068
006A
Addr
0060
0068
006A
SFR
SFR
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
004C
Addr
0048
004A
004E
0050
SFR
0052
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE
CN15IE
Bit 15
Bit 15
CPU CORE REGISTERS MAP (CONTINUED)
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12MC202
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12MC201
—
—
—
—
—
—
BREN
Bit 15
—
CN14PUE CN13PUE CN12PUE CN11PUE
CN30PUE CN29PUE
CN14IE
CN30IE
CN30PUE CN29PUE
Bit 14
CN14IE
CN30IE
Bit 14
Bit 14
—
CN13IE
CN29IE
CN13IE
CN29IE
Bit 13
Bit 13
Bit 13
CN12IE
CN12IE
Bit 12
Bit 12
—
—
—
—
Bit 12
CN27PUE
CN11IE
CN27IE
CN11IE
Bit 11
Bit 11
—
—
Bit 11
Bit 10
Bit 10
—
—
—
—
—
—
—
—
Bit 10
Bit 9
Bit 9
—
—
—
—
—
—
—
—
Bit 9
CN24PUE CN23PUE CN22PUE CN21PUE
CN24IE
Bit 8
Bit 8
—
—
—
—
XS<15:1>
XE<15:1>
YS<15:1>
YE<15:1>
—
—
Bit 8
Disable Interrupts Counter Register
CN23PUE CN22PUE CN21PUE
CN23IE
CN7PUE
Bit 7
CN23IE
CN7IE
—
—
Bit 7
XB<14:0>
Bit 7
CN22IE
CN6PUE
CN22IE
Bit 6
CN6IE
Bit 6
—
—
Bit 6
CN5PUE
CN21IE
CN5PUE
CN5IE
CN21IE
Bit 5
CN5IE
Bit 5
Bit 5
CN4PUE
CN4PUE
CN4IE
CN4IE
Bit 4
Bit 4
—
—
—
—
Bit 4
CN3PUE
CN3PUE
CN3IE
CN3IE
Bit 3
Bit 3
Bit 3
—
—
—
—
CN2PUE
CN2PUE
CN2IE
CN2IE
Bit 2
Bit 2
Bit 2
—
—
—
—
CN1PUE
CN1PUE
CN1IE
Bit 1
CN1IE
Bit 1
Bit 1
—
—
—
—
CN16PUE
CN0PUE
CN0PUE
Bit 0
CN16IE
CN0IE
CN0IE
Bit 0
Bit 0
0
1
0
1
—
—
Resets
xxxx
xxxx
xxxx
xxxx
xxxx
Resets
xxxx
Resets
All
0000
0000
0000
0000
0000
0000
0000
0000
All
All