PIC24HJ64GP206-I/PT Microchip Technology, PIC24HJ64GP206-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC24HJ64GP206-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP206-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 13
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 18 Channel
• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 8KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24HJXXXGPX06/X08/X10
10. ECAN™ Module
11. ECAN Module
12. ECAN Module Loopback Mode
13. I
14. INT0, ADC and Sleep/Idle Mode
15. Doze Mode and Traps
16. JTAG Programming
17. UART
18. UART
19. UART
20. UART
21. UART
22. UART
23. I
DS80280G-page 2
ECAN transmissions may be incorrect if multiple
transmit buffers are simultaneously queued for
transmission.
Under specific conditions, the first five bits of a
transmitted identifier may not match the value in
the transmit buffer ID register.
The ECAN module (ECAN1 or ECAN2) does not
function correctly in Loopback mode.
The Bus Collision Status bit does not get set when
a bus collision occurs during a Restart or Stop
event.
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep or Idle mode if the
SMPI bits are non-zero.
The address error trap, stack error trap, math error
trap and DMA error trap will not wake-up a device
from Doze mode.
JTAG programming does not work.
With the parity option enabled, a parity error may
occur if the Baud Rate Generator (BRG) contains
an odd value.
The Receive Buffer Overrun Error Status bit may
get set before the UART FIFO has overflowed.
UART receptions may be corrupted if the BRG is
set up for 4x mode.
The UTXISEL0 bit is always read back as zero.
The auto-baud feature may not calculate the
correct baud rate when the BRG is set up for 4x
mode.
With the auto-baud feature selected, the sync
break character (0x55) may be loaded into the
FIFO as data.
A write collision does not prevent the transmit
register from being written.
2
2
C™ Module
C Module
24. I
25. I
26. Traps and Idle Mode
27. MCLR Wake-up from Sleep Mode
28. ECAN Module
29. FRC Oscillator
30. SPI Module
31. UART
32. Device ID Register
33. DMA Module
34. Doze Mode and Traps
35. Output Compare Module
36. UART
37. UART
The ACKSTAT bit only reflects the received
ACK/NACK status for Master transmissions, but
not for Slave transmissions.
The D_A Status bit does not get set on a slave
write to the transmit register.
If a clock failure occurs when the device is in Idle
mode, the oscillator failure trap does not vector to
the Trap Service Routine (TSR).
An MCLR wake-up from Sleep mode does not wait
for the on-chip voltage regulator to power-up.
The C1RXOVF2 and C2RXOVF2 registers always
read back as 0x0000.
Internal FRC accuracy parameters are not within
the published data sheet specifications.
SPI1 functionality for pin 34 (U1RX/SDI1/RF2) is
erroneously enabled by the SPI2 module.
The auto-baud feature measures baud rate inac-
curately for certain baud rate and clock speed
combinations.
The content of the Device ID register changes
from the factory programmed value.
DMA data transfers that are active in Single-Shot
mode while the device is in Sleep or Idle mode
may result in more data transfers than expected.
A DMA error trap may not be generated when the
device is in Doze mode.
In Dual Compare Match mode, the OCx output is
not reset when the OCxR and OCxRS registers
are loaded with values having a difference of 1.
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
When an auto-baud is detected, the receive
interrupt may occur twice.
2
2
C Module
C Module
© 2008 Microchip Technology Inc.