PIC24HJ64GP206-I/PT Microchip Technology, PIC24HJ64GP206-I/PT Datasheet - Page 8

• Manufacturer Part Number: PIC24HJ64GP206-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP206-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 13
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 18 Channel
• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 8KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24HJXXXGPX06/X08/X10
8. Module: SPI in Slave Select Mode
DS80280G-page 8
The SPI module Slave Select functionality
(enabled by setting SSEN = 1) will not function
correctly. Whether the SSx pin (x = 1 or 2) is high
or low, the SPI data transfer will be completed and
an interrupt will be generated.
Work around
If DMA is not being used, poll the SSx pin state
using the Change Notification (CN) pin associated
to the SSx pin as follows:
1. Disable the SPIx module by clearing the
2. Clear the SSEN bit in the SPIxCON1 register
3. Ensure that the CNx pin is configured as a
4. Enable interrupts for the selected CNx pin by
5. Turn on the weak pull-up device for the
6. Clear the CNIF interrupt flag in the IFSx
7. Select the desired interrupt priority for CNx
8. Enable CNx interrupts using the CNIE control
9. In the CNx Interrupt Service Routine, read the
If DMA is being used, no work around exists.
SPIEN bit in the SPIxSTAT register.
to allow the I/O port to control the SSx pin.
digital input by setting the associated bit in the
TRISx register.
setting the appropriate bits in the CNEN1 and
CNEN2 registers.
selected CNx pins by setting the appropriate
bits in the CNPU1 and CNPU2 registers.
register.
interrupts using the CNIP<2:0> control bits in
the IPCx register.
bit in the IECx register.
PORTx register associated to the SSx pin:
a) If the PORTx bit is ‘0’, then enable the
b) If the PORTx bit is ‘1’, then disable the
SPIx module by setting the SPIEN bit and
perform the required data read/write.
SPIx module by setting the SPIEN bit,
clear the SPI interrupt flag (SPIxIF),
perform a dummy read of the SPIxBUF
register and return from the Interrupt
Service Routine (ISR).
9. Module: SPI
10. Module: ECAN
11. Module: ECAN
12. Module: ECAN Loopback Mode
The SMP bit (SPIxCON1<9>, where x = 1 or 2)
does not have any effect when the SPI module is
configured for a 1:1 prescale factor in Master
mode. In this mode, whether the SMP bit is set or
cleared, the data is always sampled at the end of
data output time.
Work around
If sampling at the middle of data output time is
required, then configure the SPI module to use a
clock prescale factor other than 1:1 using the
PPRE<1:0>
SPIxCON1 register.
If multiple ECAN transmit buffers are enabled
(multiple TXREQ or TXEN bits are set to ‘1’
simultaneously), then the message transmissions
from the enabled buffers may interfere with one
another. As a result, incorrect ID and data
transmissions will occur intermittently.
Work around
Enable only Buffer 0 for transmission at any given
time. In the user application, this can be ensured
by checking that all other TXREQn and TXENn
bits are clear, before setting the TXREQn bit or
TXENn to Buffer 0.
Under specific conditions, the first five bits of a
transmitted identifier may not match the value in
the transmit buffer SID. If the ECAN module
detects a Start-of-Frame (SOF) in the third bit of
interframe space and if a message to be
transmitted is pending, the first five bits of the
transmitted identifier may be corrupted.
Work around
None.
The ECAN module (ECAN1 or ECAN2) does not
function correctly in Loopback mode.
Work around
Do not use Loopback mode.
and
© 2008 Microchip Technology Inc.
SPRE<2:0>
bits
in
the