PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet
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... High-Performance, © 2009 Microchip Technology Inc. PIC18F97J60 Family 1-Mbit Flash Microcontrollers Data Sheet with Ethernet DS39762E ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... External Memory Bus (100-pin devices only): • Address Capability Mbytes • 8-Bit or 16-Bit Interface • 12-Bit, 16-Bit and 20-Bit Addressing modes © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Peripheral Highlights: • High-Current Sink/Source: 25 mA/ PORTB and PORTC • Five Timer modules (Timer0 to Timer4) • ...
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... PIC18F66J60 64K 3808 8192 PIC18F66J65 96K 3808 8192 PIC18F67J60 128K 3808 8192 PIC18F86J60 64K 3808 8192 PIC18F86J65 96K 3808 8192 PIC18F87J60 128K 3808 8192 PIC18F96J60 64K 3808 8192 PIC18F96J65 96K 3808 8192 PIC18F97J60 128K 3808 8192 DS39762E-page 4 MSSP 10-Bit CCP/ I/O ...
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... Pin Diagrams 64-Pin TQFP RE1/P2C 1 RE0/P2D 2 RB0/INT0/FLT0 3 RB1/INT1 4 RB2/INT2 5 6 RB3/INT3 MCLR 7 RG4/CCP5/P1D DDCORE CAP RF7/SS1 11 RF6/AN11 12 RF5/AN10/CV 13 REF RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY PIC18F66J60 41 PIC18F66J65 40 PIC18F67J60 DDRX TPIN+ TPIN- V SSRX RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC V SS OSC2/CLKO OSC1/CLKI ...
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... RF2/AN7/C1OUT 18 (2) 19 RH7/AN15/P1B (2) 20 RH6/AN14/P1C Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting. 2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting. DS39762E-page PIC18F86J60 PIC18F86J65 PIC18F87J60 DDRX 59 TPIN+ 58 TPIN SSRX 56 RG0/ECCP3/P3A 55 RG1/TX2/CK2 54 RB4/KBI0 53 RB5/KBI1 ...
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... RF3/AN8 22 RF2/AN7/C1OUT 23 (2) 24 RH7/AN15/P1B (2) RH6/AN14/P1C 25 Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings. 2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY PIC18F96J60 64 PIC18F96J65 ...
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... Electrical Characteristics .......................................................................................................................................................... 417 28.0 Packaging Information.............................................................................................................................................................. 453 Appendix A: Revision History............................................................................................................................................................. 463 Appendix B: Device Differences......................................................................................................................................................... 464 Index .................................................................................................................................................................................................. 465 The Microchip Web Site ..................................................................................................................................................................... 477 Customer Change Notification Service .............................................................................................................................................. 477 Customer Support .............................................................................................................................................................................. 477 Reader Response .............................................................................................................................................................................. 478 Product Identification System............................................................................................................................................................. 479 DS39762E-page 8 © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY DS39762E-page 9 ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 10 © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F66J60 • PIC18F87J60 • PIC18F66J65 • PIC18F96J60 • PIC18F67J60 • PIC18F96J65 • PIC18F86J60 • PIC18F97J60 • PIC18F86J65 This family introduces a new line of low-voltage devices with the foremost traditional advantage of all PIC18 microcontrollers – ...
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... All other features for devices in this family are identical. These are summarized in Table 1-1, Table 1-2 and Table 1-3. The pinouts for all devices are listed in Table 1-4, Table 1-5 and Table 1-6. © 2009 Microchip Technology Inc. ...
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... Ports MSSP (1), Enhanced USART (2) Yes Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR , WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 80-Pin TQFP PIC18F67J60 DC – 41.667 MHz 128K 65532 PIC18F87J60 DC – 41.667 MHz 128K 65532 DS39762E-page 13 ...
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... Ports MSSP (2), Enhanced USART (2) Yes Yes Yes 16 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR , WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 100-Pin TQFP © 2009 Microchip Technology Inc. PIC18F97J60 DC – 41.667 MHz 128K 65532 ...
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... ADC Timer0 10-Bit ECCP1 ECCP2 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Data Bus<8> Data Latch 8 8 Data Memory (3808 Bytes) PCLATU PCLATH ...
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... MCLR SS Timer1 Timer2 Timer3 Timer4 CCP4 CCP5 EUSART1 EUSART2 PORTA (1) RA0:RA5 PORTB (1) 12 RB0:RB7 4 PORTC Access Bank (1) RC0:RC7 12 PORTD (1) RD0:RD2 PORTE (1) RE0:RE7 8 PORTF PRODL (1) RF1:RF7 8 PORTG 8 8 (1) RG0:RG4 8 PORTH 8 (1) RH0:RH7 PORTJ (1) RJ4:RJ5 Comparators MSSP1 Ethernet © 2009 Microchip Technology Inc. ...
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... Timer1 10-Bit ECCP1 ECCP2 ECCP3 Note 1: See Table 1-6 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Data Latch 8 8 Data Memory (3808 Bytes) PCLATU PCLATH Address Latch ...
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... Analog input 3. I Analog A/D reference voltage (high) input. I/O ST Digital I/ Timer0 external clock input. I/O TTL Digital I/O. I Analog Analog input 4. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... PGD Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. I/O TTL Digital I/O ...
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... EUSART1 synchronous clock (see related RX1/DT1 pin). I/O ST Digital I/ EUSART1 asynchronous receive. I/O ST EUSART1 synchronous data (see related TX1/CK1 pin). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description 2 C™ mode © 2009 Microchip Technology Inc. ...
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... RD2/CCP4/P3D 58 RD2 CCP4 P3D Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O. O — ECCP1 PWM output B. I/O ST Digital I/O ...
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... ECCP2 PWM output B. I/O ST Digital I/O. O — ECCP3 PWM output C. I/O ST Digital I/O. O — ECCP3 PWM output B. I/O ST Digital I/O. O — ECCP1 PWM output C. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... RF6 AN11 RF7/SS1 11 RF7 SS1 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O. I Analog Analog input 6. O — ...
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... Ethernet differential signal output. O — Ethernet differential signal output. I Analog Ethernet differential signal input. I Analog Ethernet differential signal input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description via a resistor © 2009 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type I ST Master Clear (Reset) input ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... ECCP1 PWM output C. I/O ST Digital I/O. O — ECCP1 PWM output B. I/O ST Digital I/O. I/O ST Capture 2 input/Compare 2 output/PWM2 output. O — ECCP2 PWM output A. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. ...
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... Digital I/O. I/O ST Capture 4 input/Compare 4 output/PWM4 output. O — ECCP3 PWM output D. I/O ST Digital I/O. I/O ST Capture 5 input/Compare 5 output/PWM5 output. O — ECCP1 PWM output D. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTH is a bidirectional I/O port. ...
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... Ethernet differential signal output. O — Ethernet differential signal output. I Analog Ethernet differential signal input. I Analog Ethernet differential signal input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description via a resistor © 2009 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type I ST Master Clear (Reset) input ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... Synchronous serial clock input/output for I I/O ST Digital I/O. I/O TTL External memory address/data 7. I/O TTL Parallel Slave Port data. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description 2 C mode © 2009 Microchip Technology Inc. ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. ...
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... Analog input 10. O — Comparator reference voltage output. I/O ST Digital I/O. I Analog Analog input 11. I/O ST Digital I/O. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. ...
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... I/O ST Digital I/O. I Analog Analog input 14. O — ECCP1 PWM output C. I/O ST Digital I/O. I Analog Analog input 15. O — ECCP1 PWM output B. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTJ is a bidirectional I/O port. ...
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... Ethernet differential signal output. O — Ethernet differential signal output. I Analog Ethernet differential signal input. I Analog Ethernet differential signal input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description via a resistor © 2009 Microchip Technology Inc. ...
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... OSC1 Secondary Oscillator T1OSO T1OSCEN Enable T1OSI Oscillator Note 1: See Table 2-2 for OSCTUNE register configurations and their corresponding frequencies. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 2.2 Oscillator Types The PIC18F97J60 family of devices can be operated in five different oscillator modes High-Speed Crystal/Resonator 2 ...
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... EC mode, the feedback circuit is disabled). FIGURE 2-4: Clock from Ext. System and temperature range that is DD EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXJ6X /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (HS CONFIGURATION) OSC1 PIC18FXXJ6X (HS Mode) Open OSC2 © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and is read as ‘0’. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY used for Ethernet applications. No provision is made for internally generating the required Ethernet clock from a primary oscillator source of a different frequency ...
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... Figure 2-1. See Section 24.0 “Special Features of the CPU” for Configuration register details. PLL Block Clock Frequency (MHz) (Note 1) x101 31.2500 1111 20.8333 0111 41.6667 x100 20.8333 1110 13.8889 0110 25 (Default) x00x 6.2500 1011 4.1667 0011 4.1667 1010 2.7778 0010 © 2009 Microchip Technology Inc. ...
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... When FOSC2 = Internal oscillator Note 1: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
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... There is a delay of interval T Table 27-12), following POR, while the controller becomes ready to execute instructions. OSC1 Pin At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level modes (SEC_RUN and consumption are listed in (parameter 38, CSD OSC2 Pin © 2009 Microchip Technology Inc. ...
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... RC_IDLE 1 11 Note 1: IDLEN reflects its value when the SLEEP instruction is executed. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • The primary clock, as defined by the FOSC2:FOSC0 Configuration bits • ...
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... When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. oscillator has started. In such © 2009 Microchip Technology Inc. ...
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... OSC1 OST (1) T PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed Note 1024 (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY n-1 n Clock Transition (1) T PLL 1 2 n-1 n ...
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... The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or Fail-Safe Clock Monitor is enabled n-1 n Clock Transition (1) (1) OST T PLL 1 2 n-1 n Clock Transition PC OSTS bit Set © 2009 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet run- ning, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD © 2009 Microchip Technology Inc. ...
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... Sleep and Idle modes. This delay is required for the CPU to prepare for execu- tion. Instruction execution resumes on the first clock cycle following this delay. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 56 © 2009 Microchip Technology Inc. ...
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... Ripple Counter Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1 ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39762E-page 58 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Power-up Timer is DD BOR running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises above V , the Power-up Timer will execute the BOR additional time delay. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 4- (1) D ...
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... PWRT will expire. Bringing MCLR high will begin (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXJ6X device operating in parallel. T PWRT T PWRT © 2009 Microchip Technology Inc. execution immediately , V RISE < PWRT ): CASE 1 DD ...
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... FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY T PWRT , V RISE > 3. PWRT ): CASE ...
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... Reset. Table 4-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register ( POR STKPTR Register BOR STKFUL STKUNF © 2009 Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY MCLR Reset, WDT Reset, Power-on Reset, RESET Instruction, ...
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... Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY MCLR Reset, WDT Reset, Power-on Reset, RESET Instruction, ...
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... Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY MCLR Reset, WDT Reset, Power-on Reset, RESET Instruction, ...
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... Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY MCLR Reset, WDT Reset, Power-on Reset, RESET Instruction, ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 70 © 2009 Microchip Technology Inc. ...
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... Config. Words Unimplemented Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space ...
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... Section 24.1 “Configuration Bits”. TABLE 5-1: FLASH CONFIGURATION WORDS FOR PIC18F97J60 FAMILY DEVICES Program Configuration Device Memory Word Addresses (Kbytes) PIC18F66J60 PIC18F86J60 64 FFF8h to FFFFh PIC18F96J60 PIC18F66J65 PIC18F86J65 96 PIC18F96J65 PIC18F67J60 PIC18F87J60 128 PIC18F97J60 © 2009 Microchip Technology Inc. through 17FF8h to 17FFFh 1FFF8h to 1FFFFh ...
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... Address shifting disabled; address on external bus reflects the PC value bit 2-0 Unimplemented: Read as ‘0’ Note 1: Implemented on 100-pin devices only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY • The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip program memory ...
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... Yes Yes Yes (2) with Address Shifting On-Chip Memory Space 000000h On-Chip Program Memory (Top of Memory) (Top of Memory Mapped to External Memory 1FFFFFh – Space (Top of Memory) 1FFFFFh Table Read Table Write From To No Access No Access Yes Yes © 2009 Microchip Technology Inc. ...
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... TOSH TOSL 00h 1Ah 34h © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 SP1 SP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 5.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Fetch INST ( Execute INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 © 2009 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. © 2009 Microchip Technology Inc. ...
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... Bank 12 FFh 00h = 1101 Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...
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... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. (2) From Opcode © 2009 Microchip Technology Inc. ...
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... This register is not available on 64-pin devices. 4: This register is not available on 64 and 80-pin devices. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Reset and Interrupt registers are described in their respective chapters, while the ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral ...
Page 84
... E91h — (2) E90h — (2) E8Fh — (2) E8Eh — (2) E8Dh — (2) E8Ch — (2) E8Bh — E8Ah MISTAT (1) E89h — (1) E88h — (1) E87h — (1) E86h — E85h MAADR2 E84h MAADR1 E83h MAADR4 E82h MAADR3 E81h MAADR6 E80h MAADR5 © 2009 Microchip Technology Inc. ...
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... In Microcontroller mode, the bits in this register are unwritable and read as ‘0’. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’. 9: Implemented in 100-pin devices in Microcontroller mode only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Bit 4 Bit 3 Bit 2 Top-of-Stack Register Upper Byte (TOS< ...
Page 86
... CCP2M0 64, 193 0000 0000 xxxx xxxx 64, 189 64, 189 xxxx xxxx CCP3M0 64, 193 0000 0000 PSS1BD0 64, 205 0000 0000 CVR1 CVR0 64, 345 0000 0000 CM1 CM0 0000 0111 64, 339 64, 179 xxxx xxxx 64, 179 xxxx xxxx © 2009 Microchip Technology Inc. ...
Page 87
... In Microcontroller mode, the bits in this register are unwritable and read as ‘0’. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’. 9: Implemented in 100-pin devices in Microcontroller mode only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Bit 4 Bit 3 Bit 2 ...
Page 88
... C Master mode) 67, 269 0000 0000 UA BF 0000 0000 67, 260 SSPM1 SSPM0 67, 261, 0000 0000 271 RSEN SEN 67, 272 0000 0000 (4) ADMSK1 SEN xxxx xxxx 67, 213 TXERIF RXERIF 67, 231 -000 0-00 — — 67, 218 100- ---- © 2009 Microchip Technology Inc. ...
Page 89
... In Microcontroller mode, the bits in this register are unwritable and read as ‘0’. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’. 9: Implemented in 100-pin devices in Microcontroller mode only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Bit 4 Bit 3 Bit 2 ...
Page 90
... MARXEN 69, 219 ---0 0000 69, 248 0001 0000 0000 0000 69, 248 FCEN0 69, 248 ---- -000 BUSY 69, 222 ---- 0000 69, 235 0000 0000 69, 235 0000 0000 0000 0000 69, 235 69, 235 0000 0000 69, 235 0000 0000 69, 235 0000 0000 © 2009 Microchip Technology Inc. ...
Page 91
... For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY register then reads back as ‘000u u1uu’ recom- ...
Page 92
... EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue © 2009 Microchip Technology Inc. ...
Page 93
... FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
Page 94
... The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. © 2009 Microchip Technology Inc. ...
Page 95
... Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 5.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE ...
Page 96
... FSR2H F00h Bank 15 F40h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 060h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F40h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. 00h 60h Valid Range for ‘f’ FFh ffffffff FSR2L ffffffff ...
Page 97
... F00h BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any indirect or ...
Page 98
... PIC18F97J60 FAMILY NOTES: DS39762E-page 98 © 2009 Microchip Technology Inc. ...
Page 99
... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 100
... Reset write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Reading Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
Page 101
... Initiates a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software Write cycle complete bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-0 R/W-x R/W-0 FREE ...
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... Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 Table Erase TBLPTR<20:10> Table Write TBLPTR<20:6> Table Read – TBLPTR<21:0> the Table Pointer register TBLPTRL 0 © 2009 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVFW TABLAT, W MOVF WORD_ODD © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 104
... The CPU will stall for duration of the erase. 8. Re-enable interrupts. its. ; load TBLPTR with the base ; address of the memory block ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2009 Microchip Technology Inc. ...
Page 105
... Set the WREN bit to enable byte writes. 4. Disable interrupts. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY An on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over most of the voltage range of the device. See parameter D132B (V ) for specific limits ...
Page 106
... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block © 2009 Microchip Technology Inc. ...
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... EEPROM Control Register 2 (not a physical register) EECON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 6.5.4 PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 24.0 “ ...
Page 108
... PIC18F97J60 FAMILY NOTES: DS39762E-page 108 © 2009 Microchip Technology Inc. ...
Page 109
... Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE ...
Page 110
... Section 7.6 “16-Bit Data Width Modes”. The WM bits have no effect when an 8-Bit Data Width mode is selected. R/W-0 U-0 U-0 WAIT0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 WM1 WM0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F97J60 FAMILY 7.2.1 ADDRESS SHIFTING ON THE EXTERNAL BUS By default, the address presented on the external bus is the value of the PC. In practical terms, this means that addresses in the external memory device below the top of on-chip memory are unavailable to the micro- controller ...
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... BA0 for the byte address line and one I/O line to select between Byte and Word mode. The other 16-Bit Data Width modes do not need BA0. JEDEC standard, static RAM memories will use the signals for byte selection. © 2009 Microchip Technology Inc. are affected; A19:A16 the ...
Page 113
... Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD15:AD0 bus ...
Page 114
... The obvious limitation to this method is that the table write must be done in pairs on a specific word even address boundary to correctly write a word location. A<20:1> 373 D<15:0> 373 cycle to an odd address JEDEC Word A<x:0> EPROM Memory D<15:0> ( Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
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... Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 116
... CF33h Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 3AABh 0E55h Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive © 2009 Microchip Technology Inc. ...
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... This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruc- tion word ...
Page 118
... Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 3Ah ABh 0Eh 55h Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive © 2009 Microchip Technology Inc. ...
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... Run mode are anticipated, user applications should provide memory access time adjustments at the lower clock speeds. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended ...
Page 120
... PIC18F97J60 FAMILY NOTES: DS39762E-page 120 © 2009 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
Page 122
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 124
... IPEN PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP © 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 125
... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Note: Interrupt flag bits are set when an interrupt ...
Page 126
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39762E-page 126 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 127
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-0 ...
Page 128
... R-0 R/W-0 R/W-0 TX1IF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 129
... A TMR1/TMR3 register capture occurred (must be cleared in software TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-0 R/W-0 U-0 r BCL1IF — ...
Page 130
... Implemented in 100-pin devices only. 2: Implemented in 80-pin and 100-pin devices only. DS39762E-page 130 R-0 R/W-0 R/W-0 (2) (2) TX2IF TMR4IF CCP5IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (2) (2) R/W-0 R/W-0 CCP4IF CCP3IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 131
... TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: Implemented in 100-pin devices in Microcontroller mode only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ ...
Page 132
... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39762E-page 132 R/W-0 R/W-0 U-0 r BCL1IE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 133
... CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: Implemented in 100-pin devices only. 2: Implemented in 80-pin and 100-pin devices only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R-0 R/W-0 R/W-0 (2) (2) TX2IE TMR4IE CCP5IE U = Unimplemented bit, read as ‘0’ ...
Page 134
... TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: Implemented in 100-pin devices in Microcontroller mode only. DS39762E-page 134 R/W-1 R/W-1 R/W-1 TX1IP SSP1IP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 135
... Unimplemented: Read as ‘0’ bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-1 R/W-1 U-0 r BCL1IP — Unimplemented bit, read as ‘0’ ...
Page 136
... Implemented in 100-pin devices only. 2: Implemented in 80-pin and 100-pin devices only. DS39762E-page 136 R/W-1 R/W-1 R/W-1 (2) (2) TX2IP TMR4IP CCP5IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (2) (2) R/W-1 R/W-1 CCP4IP CCP3IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 137
... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...
Page 138
... Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS © 2009 Microchip Technology Inc. ...
Page 139
... TRIS Latch RD TRIS PORT © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
Page 140
... MOVWF TRISA driver and REF INITIALIZING PORTA ; Initialize PORTA by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Configure A/D ; Configure comparators ; for digital input ; Value used to ; initialize data ; direction ; Set RA<3:0> as inputs ; RA<5:4> as outputs © 2009 Microchip Technology Inc. ...
Page 141
... ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: Implemented in 80-pin and 100-pin devices only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O I/O Type O DIG LATA<0> data output; not affected by analog input. ...
Page 142
... Configuration bit. If the devices are in Microcontroller mode, the alternate assignment for ECCP2 is RE7. As with other ECCP2 configurations, the user must ensure that the TRISB<3> bit is set appropriately for the intended operation. can wake the device from © 2009 Microchip Technology Inc. ...
Page 143
... Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (100-pin devices in Extended Microcontroller mode). Default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD is enabled. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O I/O Type O DIG LATB< ...
Page 144
... RB5 RB4 RB3 RB2 LATB5 LATB4 LATB3 LATB2 TRISB5 TRISB4 TRISB3 TRISB2 INT0IE RBIE TMR0IF INT3IE INT2IE INT1IE INT3IF Reset Bit 1 Bit 0 Values on Page: RB1 RB0 66 LATB1 LATB0 66 TRISB1 TRISB0 65 INT0IF RBIF 63 INT3IP RBIP 63 INT2IF INT1IF 63 © 2009 Microchip Technology Inc. ...
Page 145
... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Note: These pins are configured as digital inputs on any device Reset ...
Page 146
... LATC<7> data output. ST PORTC<7> data input. ST Asynchronous serial receive data input (EUSART1 module). DIG Synchronous serial data output (EUSART1 module); takes priority over port data. ST Synchronous serial data input (EUSART1 module). User must configure as an input. © 2009 Microchip Technology Inc. ...
Page 147
... TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC7 LATC6 TRISC TRISC7 TRISC6 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATC4 LATC3 LATC2 TRISC5 TRISC4 TRISC3 ...
Page 148
... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2009 Microchip Technology Inc. ...
Page 149
... External memory interface I/O takes priority over all other digital and PSP I/O. 3: These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O I/O ...
Page 150
... Bit 2 (1) (1) (1) RD5 RD4 RD3 RD2 (1) (1) (1) LATD4 LATD3 LATD2 (1) (1) (1) TRISD4 TRISD3 TRISD2 LATA5 LATA4 LATA3 LATA2 Description (2) (2) (2) (2) (2) (2) Reset Bit 1 Bit 0 Values on Page: RD1 RD0 66 LATD1 LATD0 66 TRISD1 TRISD0 65 LATA1 LATA0 66 © 2009 Microchip Technology Inc. ...
Page 151
... REPU (LATA<6>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on all device Resets. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY PORTE is also multiplexed with Enhanced PWM outputs B and C for ECCP1 and ECCP3 and outputs B, C and D for ECCP2. For 80-pin and 100-pin devices, their default assignments are on PORTE< ...
Page 152
... External memory interface, address/data bit 12 output. I TTL External memory interface, data bit 12 input. O DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Description (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) © 2009 Microchip Technology Inc. ...
Page 153
... TRISE TRISE7 TRISE6 LATA RDPU REPU Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices; read as ‘0’. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O I/O Type O DIG LATE<5> data output PORTE<5> data input; weak pull-up when REPU bit is set. ...
Page 154
... MOVLW 07h ; MOVWF CMCON ; Turn off comparators MOVLW 0Fh ; MOVWF ADCON1 ; Set PORTF as digital I/O MOVLW 0CEh ; Value used to ; initialize data ; direction MOVWF TRISF ; Set RF3:RF1 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs © 2009 Microchip Technology Inc. ...
Page 155
... C1OUT CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. Note 1: Implemented on 100-pin devices only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O Type DIG LATF<0> data output; not affected by analog input. ST PORTF<0> data input; disabled when analog input enabled. ...
Page 156
... EXAMPLE 10-7: INITIALIZING PORTG CLRF PORTG ; Initialize PORTG by ; clearing output ; data latches CLRF LATG ; Alternate method ; to clear output ; data latches MOVLW 04h ; Value used to ; initialize data ; direction MOVWF TRISG ; Set RG1:RG0 as outputs ; RG2 as input ; RG4:RG3 as inputs © 2009 Microchip Technology Inc. ...
Page 157
... O = Output Input, DIG = Digital Output Schmitt Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Implemented on 80-pin and 100-pin devices only. 2: Implemented on 100-pin devices only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O Type DIG LATG<0> data output. ...
Page 158
... Implemented on 80-pin and 100-pin devices only. DS39762E-page 158 Bit 5 Bit 4 Bit 3 Bit 2 (1) (2) RG4 RG3 RG2 (1) (2) LATG4 LATG3 LATG2 (1) (2) TRISG4 TRISG3 TRISG2 Reset Bit 1 Bit 0 Values on Page: (2) (2) (2) RG1 RG0 66 (2) (2) (2) LATG1 LATG0 66 (2) (2) (2) TRISG1 TRISG0 65 © 2009 Microchip Technology Inc. ...
Page 159
... PORTH. All pins on PORTH are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY When the external memory interface is enabled, four of the PORTH pins function as the high-order address lines for the interface. The address output from the interface takes priority over other digital I/O ...
Page 160
... May be configured for tri-state during Enhanced PWM shutdown events. Bit 5 Bit 4 Bit 3 Bit 2 RH5 RH4 RH3 RH2 LATH5 LATH4 LATH3 LATH2 TRISH5 TRISH4 TRISH3 TRISH2 Description Reset Bit 1 Bit 0 Values on Page: RH1 RH0 66 LATH1 LATH0 65 TRISH1 TRISH0 65 © 2009 Microchip Technology Inc. ...
Page 161
... Note: These pins are configured as digital inputs on any device Reset. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY When the external memory interface is enabled, all of the PORTJ pins function as control outputs for the interface. This occurs automatically when the interface is enabled by clearing the EBDIS control bit (MEMCON< ...
Page 162
... Bit 4 Bit 3 Bit 2 (1) (1) RJ5 RJ4 RJ3 RJ2 (1) LATJ4 LATJ3 LATJ2 (1) TRISJ4 TRISJ3 TRISJ2 RA4 RA3 RA2 Description Reset Bit 1 Bit 0 Values on Page: (1) (1) RJ1 RJ0 66 (1) (1) (1) LATJ1 LATJ0 65 (1) (1) (1) TRISJ1 TRISJ0 65 RA1 RA0 66 © 2009 Microchip Technology Inc. ...
Page 163
... OBF bits can be polled and the appropriate action taken. The timing for the control signals in Write and Read modes is shown in Figure 10-3 and Figure 10-4, respectively. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 10-2: PORTD AND PORTE BLOCK DIAGRAM ...
Page 164
... Unimplemented: Read as ‘0’ FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF DS39762E-page 164 R/W-0 U-0 PSPMODE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 165
... PIR1 PSPIF ADIF RC1IF PIE1 PSPIE ADIE RC1IE IPR1 PSPIP ADIP RC1IP Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 ...
Page 166
... PIC18F97J60 FAMILY NOTES: DS39762E-page 166 © 2009 Microchip Technology Inc. ...
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... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
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... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... TMR0ON T08BIT TRISA — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 170 © 2009 Microchip Technology Inc. ...
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... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... Special Event Trigger) 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... TIMER1 OSCILLATOR C1 PIC18F97J60 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. C1 Type ( kHz 27 pF ...
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... Assuming that Timer1 is being used as a Real-Time Clock, the clock source is a 32.768 kHz crystal oscillator. In this case, one-half period of the clock is 15.25 μs. © 2009 Microchip Technology Inc. ...
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... Timer1 Register High Byte T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 176 © 2009 Microchip Technology Inc. ...
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... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSP1IF CCP1IF TX1IE SSP1IE CCP1IE TX1IP SSP1IP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSPx) PR2 8 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 63 TMR2IF TMR1IF 65 TMR2IE TMR1IE 65 TMR2IP TMR1IP © 2009 Microchip Technology Inc. ...
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... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1). It also selects the clock source options for the CCPx and ECCPx modules ...
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... RC1/T1OSI and 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’ reserved. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 182 © 2009 Microchip Technology Inc. ...
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... Timer4 is off bit 1-0 T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 15.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is readable and writable and is cleared on any device Reset ...
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... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX2IP TMR4IP CCP5IP TX2IF TMR4IF CCP5IF TX2IE TMR4IE CCP5IE Set TMR4IF TMR4 Output (to PWM) PR4 8 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 63 CCP4IP CCP3IP 65 CCP4IF CCP3IF 65 CCP4IE CCP3IE © 2009 Microchip Technology Inc. ...
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... Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Reserved 11xx = PWM mode © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY register. For the sake of clarity, all CCPx module oper- ation in the following sections is described with respect to CCP4, but is equally applicable to CCP5 ...
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... Timer3 is used for all Capture and Compare operations for all CCPx modules. Timer4 is used for PWM operations for all CCPx modules. Modules may share either timer resource as a common time base. Timer1 and Timer2 are not available. timer are in © 2009 Microchip Technology Inc. ...
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... CCP4CON<3:0> Q1:Q4 CCP5CON<3:0> CCP5 Pin Prescaler ÷ © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 16.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
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... Only a CCPx interrupt is generated, if enabled and the CCPxIE bit is set. Set CCP4IF Compare Output Match Logic 4 CCP4CON<3:0> T3CCP2 Set CCP5IF Compare Output Match Logic 4 CCP5CON<3:0> CCP4 pin TRIS Output Enable CCP5 pin TRIS Output Enable © 2009 Microchip Technology Inc. ...
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... Legend: — = unimplemented, read as ‘0’ reserved. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: This bit is only available in 80-pin and 100-pin devices; otherwise unimplemented and reads as ‘0’. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Bit 5 Bit 4 Bit 3 ...
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... CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. • OSC (TMR2 Prescale Value) “Timer2 Module” and L:CCP CON<5:4>) • • (TMRx Prescale Value) OSC © 2009 Microchip Technology Inc. ...
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... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 16.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCPx module for PWM operation: 1. ...
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... DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 Reset Bit 2 Bit 1 Bit 0 Values on Page: INT0IF RBIF 63 PD POR BOR 64 TMR2IF TMR1IF 65 TMR2IE TMR1IE 65 TMR2IP TMR1IP 65 CCP4IF CCP3IF 65 CCP4IE CCP3IE 65 CCP4IP CCP3IP 65 TRISG1 TRISG0 © 2009 Microchip Technology Inc. ...
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... PWM mode; PxA, PxC active-low; PxB, PxD active-low Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY The control register for the Enhanced CCPx module is shown in Register 17-1. It differs from the CCP4CON/ CCP5CON registers in that the two Most Significant bits are implemented to control PWM functionality ...
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... Timers depending on the mode selected. Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. Additional details on timer resources are provided in Section 16.1.1 “CCPx/ECCPx Modules and Timer Resources”. © 2009 Microchip Technology Inc. ...
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... Compatible CCP ECCP2 00xx 11xx Dual PWM 10xx 11xx Quad PWM x1xx 11xx Legend Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY RD0 or RC2 RE5 (1) RE6 ECCP1 RD0/RE6 ...
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... RD2/RG3 RH5/AN13 RH4/AN12 RD2/RG3 RH5/AN13 RH4/AN12 P3D RH5/AN13 RH4/AN12 RD2/RG3 RH5/AN13 RH4/AN12 RD2/RG3 P3B RH4/AN12 P3D P3B P3C RD2/RG3 RH5/AN13 RH4/AN12 RD2/RG3 RH5/AN13 RH4/AN12 RD2/RG3 RH5/AN13 RH4/AN12 CCP” mode Tables 17-1 for PWM Operation” or © 2009 Microchip Technology Inc. ...
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... PR2 Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead, offset by ...
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... The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 17-2. ) bits 9.77 kHz 39.06 kHz FFh FFh 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2009 Microchip Technology Inc. ...
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... OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 17.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 0 Duty Cycle Period (1) (1) Delay Delay ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ PIC18F97J60 FET Driver P1A FET Driver P1B V- V+ FET Driver Load FET Driver V- HALF-BRIDGE PWM OUTPUT Period Period td (1) ( Load + V - FET Driver FET Driver © 2009 Microchip Technology Inc. ...