PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 226

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
REGISTER 18-11: PHCON2: PHY CONTROL REGISTER 2
DS39762E-page 226
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-9
bit 8
bit 7-5
bit 4
bit 3-0
Note:
R/W-0
U-0
—
r
Improper Ethernet operation may result if HDLDIS or RXAPDIS is cleared, which is the Reset default.
Always initialize these bits set before using the Ethernet module.
Unimplemented: Read as ‘0’
FRCLNK: PHY Force Linkup bit
1 = Force linkup even when no link partner is detected (transmission is always allowed)
0 = Normal operation (PHY blocks transmission attempts unless a link partner is attached)
Reserved: Write as ‘0’
HDLDIS: PHY Half-Duplex Loopback Disable bit
1 = Normal PHY operation
0 = Reserved
Reserved: Write as ‘0’
RXAPDIS: RX+/RX- Operating mode bit
1 = Normal operation
0 = Reserved
Reserved: Write as ‘0’
FRCLNK
R/W-0
R/W-0
r
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
r
r
RXAPDIS
R/W-0
R/W-0
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
r
r
R/W-0
R/W-0
r
r
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
r
r
HDLDIS
R/W-0
R/W-0
r
bit 8
bit 0