PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 57

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.0
The PIC18F97J60 family of devices differentiates
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
This section discusses Resets generated by hard
events (MCLR), power events (POR and BOR) and
Configuration Mismatches (CM). It also covers the
operation of the various start-up timers. Stack Reset
events are covered in Section 5.1.6.4 “Stack Full and
Underflow Resets”. WDT Resets are covered in
Section 24.2 “Watchdog Timer (WDT)”.
FIGURE 4-1:
© 2009 Microchip Technology Inc.
Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
MCLR
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Power-on Reset (POR)
Brown-out Reset (BOR)
Configuration Mismatch (CM)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
Watchdog Timer (WDT) Reset during execution
V
DD
RESET
Configuration Word Mismatch
voltage regulator when there is insufficient source voltage to maintain regulation.
Pointer
Stack
PWRT
( )_IDLE
V
Brown-out
Time-out
INTRC
Reset
32 μs
DD
Detect
WDT
Sleep
Rise
External Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
RESET Instruction
(1)
POR Pulse
PWRT
11-Bit Ripple Counter
66 ms
PIC18F97J60 FAMILY
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
4.1
Device Reset events are tracked through the RCON
register (Register 4-1). The lower six bits of the register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be set by the event and
must be cleared by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.7 “Reset State
of Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
RCON Register
S
R
Q
DS39762E-page 57
Chip_Reset