PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 150

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
TABLE 10-9:
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
DS39762E-page 150
PORTD
LATD
TRISD
LATA
Legend: Shaded cells are not used by PORTD.
Note 1:
RD5/AD5/
PSP5/SDI2/
SDA2
RD6/AD6/
PSP6/SCK2/
SCL2
RD7/AD7/
PSP7/SS2
Legend:
Note 1:
Pin Name
Name
(1)
(1)
2:
3:
(1)
Unimplemented on 64-pin and 80-pin devices; read as ‘0’.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
These features or port pins are implemented only on 100-pin devices.
External memory interface I/O takes priority over all other digital and PSP I/O.
These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with
RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D).
TRISD7
LATD7
RD7
RDPU
Bit 7
Function
SDA2
SCK2
PSP5
PSP6
SCL2
PSP7
PORTD FUNCTIONS (CONTINUED)
SDI2
RD5
RD6
RD7
AD5
AD6
AD7
SS2
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
TRISD6
LATD6
RD6
REPU
Bit 6
Setting
TRIS
0
1
x
x
x
x
1
1
1
0
1
x
x
x
x
0
1
0
1
0
1
x
x
x
x
x
(1)
(1)
(1)
TRISD5
LATD5
RD5
LATA5
Bit 5
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
(1)
(1)
(1)
DIG-3
Type
DIG
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
TTL
TTL
I/O
ST
ST
ST
ST
ST
ST
ST
TRISD4
LATD4
RD4
LATA4
Bit 4
LATD<5> data output.
PORTD<5> data input; weak pull-up when RDPU bit is set.
External memory interface, address/data bit 5 output.
External memory interface, data bit 5 input.
PSP read output data (LATD<5>); takes priority over port data.
PSP write data input.
SPI data input (MSSP2 module).
I
I
setting.
LATD<6> data output.
PORTD<6> data input; weak pull-up when RDPU bit is set.
External memory interface, address/data bit 6 output.
External memory interface, data bit 6 input.
PSP read output data (LATD<6>); takes priority over port data.
PSP write data input.
SPI clock output (MSSP2 module); takes priority over port data.
SPI clock input (MSSP2 module).
I
I
setting.
LATD<7> data output.
PORTD<7> data input; weak pull-up when RDPU bit is set.
External memory interface, address/data bit 7 output.
External memory interface, data bit 7 input.
PSP read output data (LATD<7>); takes priority over port data.
PSP write data input.
Slave select input for MSSP2 module.
2
2
2
2
(1)
C™ data output (MSSP2 module); takes priority over port data.
C data input (MSSP2 module); input type depends on module
C clock output (MSSP2 module); takes priority over port data.
C clock input (MSSP2 module); input type depends on module
(1)
(1)
TRISD3
LATD3
RD3
LATA3
Bit 3
(1)
(1)
(1)
TRISD2
LATD2
LATA2
Bit 2
RD2
Description
TRISD1
LATD1
LATA1
Bit 1
RD1
© 2009 Microchip Technology Inc.
(2)
(2)
(2)
TRISD0
LATD0
LATA0
Bit 0
RD0
(2)
(2)
(2)
on Page:
Values
Reset
66
66
65
66