PIC24HJ64GP506-I/PT Microchip Technology, PIC24HJ64GP506-I/PT Datasheet - Page 14

• Manufacturer Part Number: PIC24HJ64GP506-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP506-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: 3-Wire/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 13
• Operating Supply Voltage: 0 V to 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 18-ch x 12-bit
• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 8KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• Embedded Interface Type: CAN, I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24H
4.0
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer)
and buffers or variables stored in RAM with minimal
CPU
automatically copy entire blocks of data, without the
user software having to read or write peripheral Special
Function Registers (SFRs) every time a peripheral
interrupt occurs. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM space.
The DMA Controller features eight identical data
transfer channels, each with its own set of control and
status registers. The UART, SPI, DCI, Input Capture,
Output Compare, ECAN™ technology and ADC
modules can utilize DMA. Each DMA channel can be
configured to copy data either from buffers stored in
DMA RAM to peripheral SFRs or from peripheral SFRs
to buffers in DMA RAM.
Each channel supports the following features:
• Word or byte-sized data transfers
• Transfers from peripheral to DMA RAM or DMA
FIGURE 4-1:
DS70166A-page 12
RAM to peripheral
Note: CPU and DMA address buses are not shown for clarity.
SRAM
intervention.
DIRECT MEMORY ACCESS
SRAM X-Bus
CPU
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
The
PORT 1
DMA RAM
DMA
CPU Peripheral DS Bus
Peripheral
Non-DMA
Ready
PORT 2
Controller
DMA DS Bus
can
Preliminary
DMA Controller
• Indirect addressing of DMA RAM locations with or
• Peripheral Indirect Addressing – In some
• One-Shot Block Transfers – Terminating DMA
• Continuous Block Transfers – Reloading DMA
• Ping-Pong Mode – Switching between two DMA
• Automatic or manual initiation of block transfers
• Each channel can select from 32 possible
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled. Additionally, a DMA error trap
is generated in either of the following Fault conditions:
• DMA RAM data write collision between the CPU
• Peripheral SFR data write collision between the
without automatic post-increment
peripherals, the DMA RAM read/write addresses
may be partially derived from the peripheral
transfer after one block transfer
RAM buffer start address after every block
transfer is complete
RAM start addresses between successive block
transfers, thereby filling two buffers alternately
sources of data sources or destinations
and a peripheral
CPU and the DMA Controller
Channels
DMA
Peripheral Indirect Address
Peripheral 1
CPU
Ready
DMA
© 2005 Microchip Technology Inc.
DMA
Peripheral 3
CPU
Ready
DMA
DMA
Peripheral 2
CPU
Ready
DMA
DMA