DSPIC30F5011-20I/PT Microchip Technology, DSPIC30F5011-20I/PT Datasheet - Page 44

• Manufacturer Part Number: DSPIC30F5011-20I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5011-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F5011-20I/PTG; DSPIC30F501120/PT; DSPIC30F501120IPT; DSPIC30F501120IPT

dsPIC30F5011/5013
5.2.3
Modulo addressing can be applied to the Effective
Address (EA) calculation associated with any W regis-
ter. It is important to realize that the address boundar-
ies check for addresses less than, or greater than, the
upper (for incrementing buffers), and lower (for decre-
menting buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump beyond
boundaries and still be adjusted correctly.
5.3
Bit-reversed addressing is intended to simplify data re-
ordering for radix-2 FFT algorithms. It is supported by
the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
5.3.1
Bit-reversed addressing is enabled when:
1.
2.
3.
FIGURE 5-2:
DS70116J-page 44
Note:
b15 b14 b13 b12
b15 b14 b13 b12
BWM (W register selection) in the MODCON
register is any value other than ‘15’ (the stack
cannot
addressing) and
the BREN bit is set in the XBREV register and
the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
Bit-Reversed Addressing
MODULO ADDRESSING
APPLICABILITY
The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (e.g., [W7 + W2])
is used, modulo address correction is per-
formed but the contents of the register
remain unchanged.
BIT-REVERSED ADDRESSING
IMPLEMENTATION
be
accessed
b11 b10 b9
BIT-REVERSED ADDRESS EXAMPLE
b11 b10 b9 b8
using
b8
bit-reversed
b7 b6 b5 b4
b7 b6 b5 b1
Pivot Point
b3 b2 b1
b2 b3 b4
Sequential Address
Bit-Reversed Address
If the length of a bit-reversed buffer is M = 2
then the last ‘N’ bits of the data buffer start address
must be zeros.
XB<14:0> is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, bit-reversed addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word sized data writes.
It will not function for any other addressing mode or for
byte sized data, and normal addresses will be gener-
ated instead. When bit-reversed addressing is active,
the W address pointer will always be added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the
LSb of the EA is ignored (and always clear).
If bit-reversed addressing has already been enabled by
setting the BREN (XBREV<15>) bit, then a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
Note:
Note:
XB = 0x0008 for a 16-word Bit-Reversed Buffer
0
0
All bit-reversed EA calculations assume
word sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Modulo
addressing
together. In the event that the user
attempts to do this, bit-reversed address-
ing will assume priority when active for the
X WAGU, and X WAGU modulo address-
ing will be disabled. However, modulo
addressing will continue to function in the X
RAGU.
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
addressing
© 2011 Microchip Technology Inc.
should
not
and
be
bit-reversed
enabled
N
bytes,