AT91SAM7L64-AU Atmel, AT91SAM7L64-AU Datasheet - Page 324

• Manufacturer Part Number: AT91SAM7L64-AU
• Description: MCU ARM7 64K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L64-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxx
• No. Of I/o's: 80
• Ram Memory Size: 6KB
• Cpu Speed: 36MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 29-6. Master Write with One Data Byte
Figure 29-7. Master Write with Multiple Data Byte
Figure 29-8. Master Write with One Byte Internal Address and Multiple Data Bytes
29.7.5
324
TXCOMP
TXCOMP
TXRDY
TXRDY
TWD
TWD
Write THR (Data n)
AT91SAM7L128/64 Preliminary
Master Receiver Mode
S
Write THR (Data n)
S
DADR
TXCOMP
DADR
TXRDY
TWD
When no more data is written into the TWI_THR, the master generates a stop condition to end
the transfer. The end of the complete transfer is marked by the TWI_TXCOMP bit set to one.
See
TXRDY is used as Transmit Ready for the PDC transmit channel.
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
W
Write THR (DATA)
S
Figure
W
A
29-6,
DADR
IADR(7:0)
A
Figure
Write THR (Data n+1)
DATA n
W
29-7, and
A
A
DATA n
Write THR (Data n+1)
A
Figure
DATA
29-8.
A
Write THR (Data n+x)
DATA n+5
Last data sent
(ACK received and TXRDY = 1)
A
STOP sent automaticaly
Write THR (Data n+x)
DATA n+5
Last data sent
P
A
A
DATA n+x
(ACK received and TXRDY = 1)
(ACK received and TXRDY = 1)
STOP sent automaticaly
DATA n+x
STOP sent automaticaly
6257A–ATARM–20-Feb-08
A
A
P
P