DSPIC30F6014A-30I/PT Microchip Technology, DSPIC30F6014A-30I/PT Datasheet - Page 30

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DSPIC30F6014A-30I/PT

Manufacturer Part Number
DSPIC30F6014A-30I/PT
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F6014A-30I/PT

Program Memory Type
FLASH
Program Memory Size
144KB (48K x 24)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
68
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F6014A30IP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F6014A-30I/PT
Manufacturer:
CIRRUS
Quantity:
240
Part Number:
DSPIC30F6014A-30I/PT
Manufacturer:
Microchip Technology
Quantity:
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dsPIC30F6011A/6012A/6013A/6014A
3.1.1
This architecture fetches 24-bit wide program memory.
Consequently,
However, as the architecture is modified Harvard, data
can also be present in program space.
There are two methods by which program space can
be accessed: via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 “Data
Access From Program Memory using Program
Space Visibility”). The TBLRDL and TBLWTL instruc-
tions offer a direct method of reading or writing the lsw
of any address within program space, without going
through data space. The TBLRDH and TBLWTH instruc-
tions are the only method whereby the upper 8 bits of a
program space word can be accessed as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the Least Significant
Data Word, and TBLRDH and TBLWTH access the
space which contains the Most Significant Data Byte.
Figure 3-3 shows how the EA is created for table oper-
ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
FIGURE 3-4:
DS70143C-page 28
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
PC Address
0x000000
0x000002
0x000004
0x000006
instructions
PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
00000000
00000000
00000000
00000000
are
always
23
aligned.
TBLRDL.W
Preliminary
16
A set of table instructions are provided to move byte or
word sized data to and from program space.
1.
2.
3.
4.
TBLRDL: Table Read Low
Word: Read the lsw of the program address;
P<15:0> maps to D<15:0>.
Byte: Read one of the LSBs of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> maps to the destination byte when byte
select = 1.
TBLWTL: Table Write Low (refer to Section 6.0
“Flash Program Memory” for details on Flash
Programming)
TBLRDH: Table Read High
Word: Read the most significant word of the pro-
gram address; P<23:16> maps to D<7:0>;
D<15:8> will always be = 0.
Byte: Read one of the MSBs of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
TBLWTH: Table Write High (refer to Section 6.0
“Flash Program Memory” for details on Flash
Programming).
TBLRDL.B (Wn<0> = 1)
8
TBLRDL.B (Wn<0> = 0)
© 2006 Microchip Technology Inc.
0

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