DSPIC30F6014A-30I/PT Microchip Technology, DSPIC30F6014A-30I/PT Datasheet - Page 55

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DSPIC30F6014A-30I/PT

Manufacturer Part Number
DSPIC30F6014A-30I/PT
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F6014A-30I/PT

Program Memory Type
FLASH
Program Memory Size
144KB (48K x 24)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
68
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F6014A30IP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
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DSPIC30F6014A-30I/PT
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CIRRUS
Quantity:
240
Part Number:
DSPIC30F6014A-30I/PT
Manufacturer:
Microchip Technology
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6.6
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 2 msec in
duration and the processor stalls (waits) until the oper-
ation is finished. Setting the WR bit (NVMCON<15>)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
6.6.1
The user can erase and program one row of program
Flash memory at a time. The general process is:
1.
2.
3.
EXAMPLE 6-1:
© 2006 Microchip Technology Inc.
; Setup NVMCON for erase operation, multi word write
; program memory selected, and writes enabled
; Init pointer to row to be ERASED
Read one row of program Flash (32 instruction
words) and store into data RAM as a data
“image”.
Update the data image with the desired new
data.
Erase program Flash row.
a)
b)
c)
d)
e)
f)
g)
Programming Operations
Setup NVMCON register for multi-word,
program Flash, erase, and set WREN bit.
Write address of row to be erased into
NVMADRU/NVMADR.
Write ‘55’ to NVMKEY.
Write ‘AA’ to NVMKEY.
Set the WR bit. This will begin erase cycle.
CPU will stall for the duration of the erase
cycle.
The WR bit is cleared when erase cycle
ends.
MOV
MOV
MOV
MOV
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
#0x4041,W0
W0
#tblpage(PROG_ADDR),W0
W0
#tbloffset(PROG_ADDR),W0
W0, NVMADR
#5
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
,
,
,
,
ERASING A ROW OF PROGRAM MEMORY
dsPIC30F6011A/6012A/6013A/6014A
NVMCON
NVMADRU
NVMKEY
NVMKEY
Preliminary
;
; Init NVMCON SFR
;
; Initialize PM Page Boundary SFR
; Intialize in-page EA[15:0] pointer
; Initialize NVMADR SFR
; Block all interrupts with priority <7 for
; next 5 instructions
; Write the 0x55 key
;
; Write the 0xAA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
4.
5.
6.
6.6.2
Example 6-1 shows a code sequence that can be used
to erase a row (32 instructions) of program memory.
Write 32 instruction words of data from data
RAM “image” into the program Flash write
latches.
Program 32 instruction words into program
Flash.
a)
b)
c)
d)
e)
f)
Repeat steps 1 through 5 as needed to program
desired amount of program Flash memory.
Setup NVMCON register for multi-word,
program Flash, program, and set WREN
bit.
Write ‘55’ to NVMKEY.
Write ‘AA’ to NVMKEY.
Set the WR bit. This will begin program
cycle.
CPU will stall for duration of the program
cycle.
The WR bit is cleared by the hardware
when program cycle ends.
ERASING A ROW OF PROGRAM
MEMORY
DS70143C-page 53

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