Z16F3211AL20SG Zilog, Z16F3211AL20SG Datasheet - Page 233

• Manufacturer Part Number: Z16F3211AL20SG
• Description: IC ZNEO MCU FLASH 32K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F3211AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F3x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 2 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4568

PS022008-0810
Slave Transactions
26. Software responds by setting the STOP bit of the I
27. A STOP condition is sent to the I
The following sections describe Read and Write transactions to the I
configured for 7-bit and 10-bit SLAVE modes.
Slave Address Recognition
The following Slave address recognition options are supported:
•
•
•
•
General Call and STARTBYTE address recognition - If
Software address recognition - To disable the hardware address recognition, the
controller is configured for Master/Slave or Slave 7-bit address mode, the hardware
detects a match to the 7-bit Slave address defined in the I2CSLVAD register and
generates the Slave Address Match interrupt (
I
the
controller is configured for Master/Slave or Slave 10-bit address mode, the hardware
detects a match to the 10-bit Slave address defined in the I2CMODE and I2CSLVAD
registers and generates the Slave Address Match interrupt (
register). The I
with the value in the
address phase and the controller is configured for Master/Slave or Slave in either 7- or
10-bit address mode, the hardware detects a match to the General Call Address or
START byte and generates the Slave Address Match interrupt. A General Call Address
is a 7-bit address of all 0’s with the R/W bit = 0. A START byte is a 7-bit address of all
0’s with the R/W bit = 1. The
RD
byte (= 0 for General Call Address). For a General Call Address, the I
automatically responds during the address acknowledge phase with the value in the
NAK
GCA
examine each received data byte before deciding to set or clear the
byte will not be acknowledged (requirement the I
must be set = 1 prior to the reception of the address byte(s). When
received byte generates a receive interrupt (
Software must examine each byte and determine whether to set or clear the
The Slave holds SCL Low during the acknowledge phase until software responds by
writing to the I2CCTL register. The value written to the
controller to drive the I
Slave 10-bit address recognition mode - If
Slave 7-bit address recognition mode - If
2
C Controller automatically responds during the acknowledge phase with the value in
bit in the I2CISTAT register distinguishes a General Call Address from a START
NAK
bit of the I2CCTL register. If software processes the data bytes associated with the
bit, the
bit of the I2CCTL register.
IRM
2
C Controller automatically responds during the acknowledge phase
bit is optionally set following the SAM interrupt to allow software to
NAK
P R E L I M I N A R Y
2
C Bus, then releasing the SCL. The
bit of the I2CCTL register.
SAM
2
C Slave.
and
GCA
IRM
IRM
bits are set in the I2CISTAT register. The
SAM
RDRF
= 0 during the address phase and the
= 0 during the address phase and the
2
C specification).
2
bit = 1 in I2CISTAT register). The
C Control register.
= 1 in the I2CISTAT register).
GCE
I
2
= 1 and
C Master/Slave Controller
SAM
SAM
Product Specification
NAK
ZNEO
2
bit = 1 in I2CISTAT
C Controller
and
bit is used by the
NAK
IRM
GCA
IRM
Z16F Series
= 0 during the
bit. A START
2
C Controller
bits are not
= 1 each
NAK
IRM
bit.
bit
217