Z16F3211AL20SG Zilog, Z16F3211AL20SG Datasheet - Page 337

• Manufacturer Part Number: Z16F3211AL20SG
• Description: IC ZNEO MCU FLASH 32K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F3211AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F3x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 2 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4568

Table 173. OCD Control Register (OCDCTL)
PS022008-0810
BITS
FIELD
RESET
R/W
OCD Control Register
DBGHALT BRKHALT
R/W
Reserved
These bits are reserved.
CRCEN—CRC enable
If this bit is set, a CRC is appended to the end of each debug command. Clearing this bit
will disable transmission of the CRC.
0 = CRC disabled
1 = CRC enabled
UARTEN—UART enable
This bit is used to enable or disable the UART. This bit is ignored when
0 = UART Disabled.
1 = UART Enabled.
ABCHAR—Auto-baud character
This bit selects the character used during auto-baud detection. This bit cannot be written
by the CPU if
0 = Auto-baud character to be measured is
1 = Auto-baud character to be measured is
ABSRCH—Auto-baud search mode
This bit enables auto-baud search mode. When this bit is set, the next character received is
measured to set the Baud Rate Reload register. This bit clears itself to zero once the reload
register has been written. This bit is automatically set when
communication error occurs. This bit cannot be written by the CPU if the
0 = Auto-baud search disabled.
1 = Auto-baud search enabled.
The
the CPU in Debug Halt Mode, enable breakpoints, or single step an instruction.
DBGHALT—Debug halt
Setting this bit to one causes the device to enter Debug Halt mode. When in Debug Halt
mode, the CPU stops fetching instructions. Clearing this bit causes the CPU to start
running again. This bit is automatically set to one when a breakpoint occurs if the
7
0
OCD Control Register (OCDCTL)
R/W
6
0
OCDEN
BRKEN
is set.
R/W
5
0
P R E L I M I N A R Y
DBGSTOP
R/W
4
0
controls the state of the CPU. This register puts
80H
0DH
.
.
3
Reserved
000
OCDEN
R
2
Product Specification
ZNEO
is set if a serial 
On-Chip Debugger
OCDEN
1
OCDEN
Z16F Series
is set.
bit is set.
STEP
R/W
0
0
321