Z16F6411AL20SG Zilog, Z16F6411AL20SG Datasheet - Page 213

• Manufacturer Part Number: Z16F6411AL20SG
• Description: IC ZNEO MCU FLASH 64K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4570

Table 102. ESPI Status Register (ESPISTAT)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
R/W* = Read access. Write a 1 to clear the bit to 0.
ESPI Status Register
TDRE
R
7
0
The ESPI Status register (see
revert to their Reset state, if the ESPI is disabled.
TDRE—Transmit Data Register Empty
0 = Transmit data register is full or ESPI is disabled.
1 = Transmit data register is empty. A write to the ESPI (Transmit) Data register clears this
bit.
TUND—Transmit Underrun
0 = A Transmit Underrun error has not occurred.
1 = A Transmit Underrun error has occurred.
COL—Collision
0 = A Multi-Master collision (mode fault) has not occurred.
1 = A Multi-Master collision (mode fault) has been detected.
ABT—Slave mode transaction abort
This bit is set if the ESPI is configured in Slave mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the ESPIMODE register. This bit is also be set in Slave mode by an SCK monitor
timeout (MMEN = 0, BRGCTL = 1).
0 = A Slave mode transaction abort has not occurred.
1 = A Slave mode transaction abort has been detected.
ROVR—Receive Overrun
0 = A Receive Overrun error has not occurred.
1 = A Receive Overrun error has occurred.
RDRF—Receive Data Register Full
0 = Receive Data register is empty.
1 = Receive Data register is full. A read from the ESPI (Receive) Data register clears
this bit.
TUND
R/W*
6
0
R/W*
COL
5
0
P R E L I M I N A R Y
Table
R/W*
ABT
4
0
102) indicates the current state of the ESPI. All bits
FF_E264H
ROVR
R/W*
3
0
Enhanced Serial Peripheral Interface
RDRF
R
2
0
Product Specification
ZNEO
TFST
R
1
0
Z16F Series
SLAS
R
0
1
197