Z16F6411AL20SG Zilog, Z16F6411AL20SG Datasheet - Page 321

• Manufacturer Part Number: Z16F6411AL20SG
• Description: IC ZNEO MCU FLASH 64K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4570

PS022008-0810
Initialization
Initialization during Reset
If the standard serial port of a PC is used, transmit flow control is enabled on the ZNEO
Z16F Series device. The PC sends the start bit when receiving data by transmitting the
character FFH. Since character FFH is also received from a non-responsive device, space
parity (parity bit always zero) must be enabled and used as an acknowledge bit.
The OCD ignores any data received until it receives the read revision command
After the read revision command is received, the remaining debug commands are issued.
The packet CRC is not sent for the first read revision command issued during
initialization.
The OCD is initialized during reset. This is done by asserting the reset pin, sending the
auto-baud character, and then issuing the read revision command. When the OCD is 
initialized during reset, the
Receiving
Device
Transmitting
Device
Single Wire
Bus
ST = Start Bit
SP = Stop Bit
D0-D7 = Data Bits
Figure 67. Start Bit Flow Control
ST
ST
D0
D0
P R E L I M I N A R Y
DBGHALT
D1
D1
D2
D2
bit in the OCDCTL register is automatically set.
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Product Specification
ZNEO
SP
SP
On-Chip Debugger
Z16F Series
00H
. 
305