Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 125

• Manufacturer Part Number: Z16F2811AL20SG
• Description: IC ZNEO MCU FLASH 128K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4533

Table 63. Timer 0-2 Control 1 Register (TxCTL1)
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
Bit Position
[3:1]
PWMD
[0]
INCAP
Bit Position
[7]
TEN
TEN
R/W
7
0
Timer 0-2 Control 1 Register
The Timer 0-2 control 1 (TxCTL1) register enables/disables the timer, sets the prescaler
value, and determines the timer operating mode.
Value (H) Description
Value (H) Description
000
001
010
100
101
011
110
111
0
1
0
1
TPOL
R/W
6
0
PWM Delay Value
This field is a programmable delay to control the number of additional system
clock cycles following a PWM or Reload compare before the timer output or
the timer output complement is switched to the active state. This field ensures
a time gap between deassertion of o ne PWM outpu t to the assertion of its
complement.
No delay.
2 cycles delay.
4 cycles delay.
8 cycles delay.
16 cycles delay.
32 cycles delay.
64 cycles delay.
128 cycles delay.
Input Capture Event
Previous timer interrupt is not a result of a timer input capture event.
Previous timer interrupt is a result of a timer input capture event.
Timer is disabled.
Timer is enabled.
Note: TEN bit is cleared automatically when the timer stops.
5
FF-E307H, FF-E317H, FF-E327H
P R E L I M I N A R Y
PRES
R/W
000
4
3
2
Product Specification
ZNEO
TMODE
R/W
000
1
Z16F Series
Timers
0
110