Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 245

• Manufacturer Part Number: Z16F2811AL20SG
• Description: IC ZNEO MCU FLASH 128K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4533

Table 110. I
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
Note:
I
2
C Control Register
2
C Control Register (I2CCTL)
R/W
IEN
7
0
The I
R/W1 - bit is set (write 1) but not cleared.
IEN—I
This bit enables the I
START—Send start condition
When set, this bit causes the I
Start condition. Once asserted, it is cleared by the I
condition or by deasserting the
the bit. After this bit is set, the START condition is sent if there is data in the I2CDATA or
I2CSHIFT register. If there is no data in one of these registers, the I
until data is loaded. If this bit is set while the I
generates a RESTART condition after the byte shifts and the acknowledge phase
completes. If the STOP bit is also set, it also waits until the STOP condition is sent before
the START condition.
If START is set while a slave mode transaction is underway to this device, the START bit
is cleared and
STOP—Send stop condition
When set, this bit causes the I
STOP condition after the byte in the I
a byte has been received in a receive operation. When set, this bit is reset by the I
Controller after a STOP condition has been sent or by deasserting the IEN bit. If this bit is
1, it cannot be cleared to 0 by writing to the register.
If STOP is set while a slave mode transaction is underway, the STOP bit will be cleared by
hardware.
BIRQ—Baud rate generator interrupt request
This bit is ignored when the I
Controller is disabled (
causing an interrupt to occur every time the baud rate generator counts down to one. The
baud rate generator runs continuously in this mode, generating periodic interrupts.
2
C Control register (see
2
START
C enable
R/W1
6
0
ARBLST
STOP
2
R/W1
C Controller.
IEN
bit in the Interrupt Status register will be set.
5
0
P R E L I M I N A R Y
= 0) the baud rate generator is used as an additional timer
2
Table
2
2
C Controller is enabled. If this bit is set = 1 when the I
C Controller (when configured as the Master) to send the
C Controller (when configured as the Master) to send the
IEN
BIRQ
R/W
4
0
110) enables and configures the I
bit. If this bit is 1, it cannot be cleared by writing to
FF-E242H
2
C Shift register has completed transmission or after
R/W
TXI
2
C Controller is shifting out data, it
3
0
2
C Controller after it sends the Start
R/W1
NAK
2
0
I
2
C Master/Slave Controller
Product Specification
ZNEO
2
FLUSH
C Controller waits
2
C operation.
R/W
1
0
Z16F Series
FILTEN
2
R/W
C
0
0
2
C
229