ST10F269Z2Q3 STMicroelectronics, ST10F269Z2Q3 Datasheet - Page 132

IC FLASH MEM 256KBIT 144-PQFP

ST10F269Z2Q3

Manufacturer Part Number
ST10F269Z2Q3
Description
IC FLASH MEM 256KBIT 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F269Z2Q3

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-QFP
Processor Series
ST10F26x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN, SSC, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
2 x 16 bit
Operating Supply Voltage
0.3 V to 4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit x 10 bit
Cpu Family
ST10
Device Core Size
16b
Frequency (max)
40MHz
Total Internal Ram Size
12KB
# I/os (max)
111
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
CISC/RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-2042

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20 - SPECIAL FUNCTION REGISTER OVERVIEW
20.2 - System Configuration Registers
The ST10F269 has registers used for different configuration of the overall system. These registers are
described below.
SYSCON (FF12h / 89h)
Notes: 1. These bit are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence.
132/184
15 14 13
XPER-SHARE
VISIBLE
XPEN
BDRSTEN
OWDDIS
PWDCFG
CSCFG
WRCFG
STKSZ
RW
2. Register SYSCON cannot be changed after execution of the EINIT instruction.
ROMS1 SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG
RW
12
XBUS Peripheral Share Mode Control
‘0’: External accesses to XBUS peripherals are disabled
‘1’: XBUS peripherals are accessible via the external bus during hold mode
Visible Mode Control
‘0’: Accesses to XBUS peripherals are done internally
‘1’: XBUS peripheral accesses are made visible on the external pins
XBUS Peripheral Enable bit
‘0’: Accesses to the on-chip X-Peripherals and XRAM are disabled
‘1’: The on-chip X-Peripherals are enabled.
Bidirectional Reset Enable
‘0’: RSTIN pin is an input pin only. (SW Reset or WDT Reset have no effect on this pin)
‘1’: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence.
Oscillator Watchdog Disable Control
‘0’: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity. If
there is no activity on XTAL1 for at least 1 s, the CPU clock is switched automatically to PLL’s
base frequency (from 2 to 10MHz).
‘1’: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The
PLL is turned off to reduce power supply current.
Power Down Mode Configuration Control
‘0’: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low,
otherwise the instruction has no effect. Exit power down only with reset.
‘1’: Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast
external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting
one enabled EXxIN pin or with external reset.
Chip Select Configuration Control
‘0’: Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE
‘1’: Unlatched Chip Select lines: CSx change with rising edge of ALE.
Write Configuration Control (Inverted copy of bit WRC of RP0H)
RW
11
RW
10
1
RW
9
1
RW
8
SFR
RW
7
1
RW
6
PWD
CFG
RW
5
OWD
RW
DIS
4
STEN
BDR
RW
3
XPEN VISIBLE
Reset Value: 0xx0h
RW
2
RW
ST10F269
1
SHARE
XPER-
RW
0

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