MC908JL3ECPE Freescale Semiconductor, MC908JL3ECPE Datasheet - Page 111

• Manufacturer Part Number: MC908JL3ECPE
• Description: IC MCU 4K FLASH 8MHZ 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL3ECPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Controller Family/series: HC08
• No. Of I/o's: 23
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

10.4.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input or an output. Writing a one to a
DDRD bit enables the output buffer for the corresponding port D pin; a zero disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
When DDRDx is a 1, reading address $0003 reads the PTDx data latch. When DDRDx is a 0, reading
address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit.
Freescale Semiconductor
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Address:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
port D I/O logic.
Reset:
Read:
Write:
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
DDRD7
$0007
Bit 7
0
Figure 10-10. Data Direction Register D (DDRD)
Table 10-4
DDRD6
MC68HC908JL3E Family Data Sheet, Rev. 4
6
0
RESET
Figure 10-11. Port D I/O Circuit
summarizes the operation of the port D pins.
DDRD5
5
0
NOTE
DDRD4
DDRDx
PTDx
4
0
DDRD3
3
0
Figure 10-11
PTD[0:3] To Analog-To-Digital Converter
PTD[4:5] To Timer
DDRD2
2
0
PTDPU[6:7]
DDRD1
1
0
shows the
5k
DDRD0
Bit 0
PTDx
0
Port D
111