MC9S08AW60MFGE Freescale Semiconductor, MC9S08AW60MFGE Datasheet - Page 103

• Manufacturer Part Number: MC9S08AW60MFGE
• Description: IC MCU 8BIT 60K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AW60MFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-LQFP
• Processor Series: S08AW
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 5.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AW60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 44LQFP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• For Use With: DEMO9S08AW60E - DEMO BOARD FOR MC9S08AW60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
1
6.7.12
In addition to the I/O control, port F pins are controlled by the registers listed below.
Freescale Semiconductor
Bits 7, 3 and 2 are reserved bits that must always be written to 0.
Bits 7, 3 and 2 are reserved bits that must always be written to 0.
PTFPEn
PTFSEn
Reset
Reset
6:4, 1:0
6:4, 1:0
Field
Field
W
W
R
R
Port F Pin Control Registers (PTFPE, PTFSE, PTFDS)
Internal Pullup Enable for Port F Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTF pin. For port F pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port F bit n.
1 Internal pullup device enabled for port F bit n.
Output Slew Rate Control Enable for Port F Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTF pin. For port F pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port F bit n.
1 Output slew rate control enabled for port F bit n.
R
R
0
0
7
7
Figure 6-38. Output Slew Rate Control Enable for Port F (PTFSE)
PTFPE6
PTFSE6
0
Figure 6-37. Internal Pullup Enable for Port F (PTFPE)
0
6
6
Table 6-28. PTFPE Register Field Descriptions
Table 6-29. PTFSE Register Field Descriptions
PTFPE5
PTFSE5
MC9S08AC16 Series Data Sheet, Rev. 8
0
0
5
5
PTFPE4
PTFSE4
0
0
4
4
Description
Description
R
R
3
0
3
0
R
R
0
0
2
2
1
Chapter 6 Parallel Input/Output
PTFPE1
PTFSE1
1
0
0
1
1
PTFPE0
PTFSE0
0
0
0
0
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