MCF52236AF50 Freescale Semiconductor, MCF52236AF50 Datasheet - Page 3

• Manufacturer Part Number: MCF52236AF50
• Description: IC MCU 32BIT 256K FLASH 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF5223xr

Specifications of MCF52236AF50

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-LQFP
• Processor Series: MCF522x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, QSPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 10
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52235EVB, M52233DEMO
• Minimum Operating Temperature: 0 C
• On-chip Adc: 12 bit, 8 Channel
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Height: 1.5 mm
• Length: 14 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1
1
Freescale Semiconductor
Version 2 ColdFire Core with EMAC
(Enhanced Multiply-Accumulate Unit)
System Clock (MHz)
Performance (Dhrystone 2.1 MIPS)
Flash / Static RAM (SRAM)
Interrupt Controllers (INTC0/INTC1)
Fast Analog-to-Digital Converter (ADC)
Random Number Generator and Crypto
Acceleration Unit (CAU)
FlexCAN 2.0B Module
Fast Ethernet Controller (FEC) with on-chip
interface (EPHY)
Four-channel Direct-Memory Access (DMA)
Software Watchdog Timer (WDT)
Programmable Interrupt Timer
Four-Channel General Purpose Timer
32-bit DMA Timers
QSPI
UART(s)
I
Eight/Four-channel 8/16-bit PWM Timer
General Purpose I/O Module (GPIO)
Chip Configuration and Reset Controller
Module
Background Debug Mode (BDM)
JTAG - IEEE 1149.1 Test Access Port
Package
2
C
The full debug/trace interface is available only on the 112- and 121-pin packages. A reduced debug interface is bonded on the
80-pin package.
MCF52235 Family Configurations
Module
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
1
Table 1. MCF52235 Family Configurations
112 LQFP
80 LQFP
128/32
Kbytes
52230
56
60
—
—
2
4
3














112 LQFP
80 LQFP
128/32
Kbytes
52231
60
56
—
2








4

3






80 LQFP
128/32
Kbytes
52232
50
46
—
—
2
4
3














112 LQFP
80 LQFP
256/32
Kbytes
52233
56
60
—
—






2

4

3






MCF52235 Family Configurations
112 LQFP
MAPBGA
256/32
Kbytes
52234
121
60
56
—
2
4
3















112 LQFP
MAPBGA
256/32
Kbytes
52235
121
60
56
2
4
3
















80 LQFP
256/32
Kbytes
52236
46
50
—
—






2

4

3






3