MC9S12XEP100CAG Freescale Semiconductor, MC9S12XEP100CAG Datasheet - Page 1052

• Manufacturer Part Number: MC9S12XEP100CAG
• Description: IC MCU 16BIT 1M FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24-ch x 12-bit
• Cpu Family: HCS12X
• Device Core Size: 16b
• Frequency (max): 50MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 25
• Operating Supply Voltage (typ): 1.8/2.8/5V
• Operating Supply Voltage (max): 1.98/2.9/5.5V
• Operating Supply Voltage (min): 1.72/2.7/3.13V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
27.4.1.4
Table 27-31
Flash block and other resources within the Flash module.
27.4.1.5
Table 27-32
on the D-Flash block and EEE operation.
1052
FCMD
FCMD
0x0C
0x0D
0x0A
0x0B
0x0E
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x01
0x02
Erase Verify Block
Erase Verify Block
Program P-Flash
summarizes the valid P-Flash commands along with the effects of the commands on the P-
summarizes the valid D-Flash and EEE commands along with the effects of the commands
Erase All Blocks
Set User Margin
Set Field Margin
Load Data Field
Unsecure Flash
Verify Backdoor
Erase Verify All
Erase Verify All
P-Flash Commands
Erase Verify P-
D-Flash and EEE Commands
Program Once
Erase P-Flash
Erase P-Flash
Flash Section
Access Key
Read Once
Command
Command
Blocks
Sector
Blocks
Block
Level
Level
Verify that all D-Flash (and P-Flash) blocks are erased.
Verify that the D-Flash block is erased.
Verify that all P-Flash (and D-Flash) blocks are erased.
Verify that a P-Flash block is erased.
Verify that a given number of words starting at the address provided are erased.
Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block 0
that was previously programmed using the Program Once command.
Load data for simultaneous multiple P-Flash block operations.
Program a phrase in a P-Flash block and any previously loaded phrases for any other P-
Flash block (see Load Data Field command).
Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block
0 that is allowed to be programmed only once.
Erase all P-Flash (and D-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are
set prior to launching the command.
Erase a single P-Flash block.
An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN
bits in the FPROT register are set prior to launching the command.
Erase all bytes in a P-Flash sector.
Supports a method of releasing MCU security by erasing all P-Flash (and D-Flash) blocks
and verifying that all P-Flash (and D-Flash) blocks are erased.
Supports a method of releasing MCU security by verifying a set of security keys.
Specifies a user margin read level for all P-Flash blocks.
Specifies a field margin read level for all P-Flash blocks (special modes only).
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 27-31. P-Flash Commands
Table 27-32. D-Flash Commands
Function on D-Flash Memory
Function on P-Flash Memory
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