MC56F8356VFVE Freescale Semiconductor, MC56F8356VFVE Datasheet
MC56F8356VFVE
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MC56F8356VFVE Summary of contents
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Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8356 Rev. 13 01/2007 freescale.com ...
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... Table 10-24 and new and clarified Section 12.3. Table 10-1; also removed overall Table Table 13-1. 10-1). Deleted formula for Max Ambient Table 2-2. Clarified external reference crys- Table 2-2. Table 2-2: Table 2- the design used in a debugging SS Freescale Semiconductor 10-4. Preliminary ...
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... Quad 2 Timer D or GPIOE 2 FlexCAN SPI0 or GPIOE 4 Freescale Semiconductor Preliminary • Temperature Sensor • two Quadrature Decoders • Optional on-chip regulator • FlexCAN module • Two Serial Communication Interfaces (SCIs) • two Serial Peripheral Interfaces (SPIs) • four general-purpose Quad Timers • ...
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... Thermal Design Considerations . . . . . . . 174 12.2 Electrical Design Considerations . . . . . . 175 12.3 Power Distribution and I/O Ring Part 13 Ordering Information . . . . . . . . . . 177 56F8356 Technical Data, Rev. 13 Interrupt Timing . . . . . . . . . . . . . . . 150 Timing 153 Timing 159 Parameters . . . . . . . . . . . . . . . . . . . 161 Information . . . . . . . . . . . . . . . . . . . 167 Information . . . . . . . . . . . . . . . . . . . 169 Implementation . . . . . . . . . . . . . . . . 176 Freescale Semiconductor Preliminary ...
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... Table 1-1 outlines the key differences between the 56F8356 and 56F8156 devices. Feature Guaranteed Speed Program RAM Data Flash PWM CAN Quad Timer Quadrature Decoder Temperature Sensor Dedicated GPIO Freescale Semiconductor Preliminary Table 1-1 Device Differences 56F8356 60MHz/60 MIPS 4KB 8KB — ...
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... Timer D with two pins — In the 56F8156, two Quad Timers; Timer A and Timer C both work in conjunction with GPIO • Optional on-chip regulator • FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive 6 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... The 56F8356 and 56F8156 support program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide two external dedicated interrupt lines and General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. Freescale Semiconductor Preliminary 56F8356 Technical Data, Rev. 13 Device Description ...
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... Program Flash memory areas, which can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot Flash page erase size is 512 bytes. and the Boot Flash memory can also be either bulk or page erased. 8 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. Freescale Semiconductor Preliminary 56F8356 Technical Data, Rev. 13 Award-Winning Development Environment ...
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... The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals. 10 Figure 1-1 and Figure 56F8356 Technical Data, Rev. 13 1-2. Figure 1-1 illustrates how the Part 2, Signal/Connection Freescale Semiconductor Preliminary ...
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... Flash memories are encapsulated within the Flash Module(FM). Flash control is accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the Flash memories. Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits. Freescale Semiconductor Preliminary pdb_m[15:0] pab[20:0] cdbw[31:0] ...
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... Technical Data, Rev. 13 Interrupt Controller Low Voltage Interrupt POR & LVI System POR RESET SIM COP Reset COP 2 FlexCAN 12 PWMA SYNC Output 13 PWMB SYNC Output ch2i ch3i 1 Timer C ch2o ch3o 8 ADCB 8 ADCA 1 TEMP_SENSE , REFH REFP , and V pins. REFN REFLO Freescale Semiconductor , REFMID Preliminary ...
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... Primary Data Memory and therefore generates no delays when accessing the processor. Write data is obtained from cdbw. Read data is provided to cdbr_m. 1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0. Freescale Semiconductor Preliminary Table 1-2 Bus Signal Names Function ...
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... Freescale Literature Distribution Table 1-3 Chip Documentation Description Logic State True False True False 56F8356 Technical Data, Rev. 13 Centers, or online Order Number DSP56800ERM MC56F8300UM MC56F83xxBLUM MC56F8356 MC56F8356E MC56F8156E Signal State 1 Voltage Asserted Deasserted Asserted Deasserted Freescale Semiconductor Preliminary at ...
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... Temperature Sense Dedicated GPIO 1. If the on-chip regulator is disabled, the V 2. Alternately, can function as Quad Timer pins or GPIO 3. Pins in this section can function as Quad Timer, SPI #1, or GPIO Freescale Semiconductor Preliminary Figure 2-1. In Table 2-2, each table row describes the signal or signals pins serve as 2 ...
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... Technical Data, Rev. 13 Quadrature Decoder 0 or Quad Timer A or GPIO SPI0 or GPIO Quadrature Decoder 1 or Quad Timer B or SPI 1 or GPIO PWMA or GPIO PWMB or GPIO ADCA ADCB Temperature Sensor FlexCAN QUAD TIMER C and D or GPIO INTERRUPT/ PROGRAM CONTROL 1 (144-pin LQFP) Freescale Semiconductor Preliminary ...
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... TXD1 (GPIOD6) SCI 1 RXD1 (GPIOD7) or GPIO JTAG/ EOnCE Port TRST Figure 2-2 56F8156 Signals Identified by Functional Group 1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. Freescale Semiconductor Preliminary DD_IO 7 PHASEA0 (TA0, GPIOC4 PHASEB0 (TA1, GPIOC5) 1 INDEX0 (TA2, GPIOC6) ...
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... OSC and to the internal regulator that in turn supplies the Phase Locked Loop. It must be connected to a clean analog power supply. V — These pins provide ground for chip logic and I/O drivers. SS ADC Analog Ground — This pin supplies an analog ground to the ADC modules. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... CLKMODE 87 Input EXTAL 82 Input XTAL 81 Input/ Output CLKO 3 Output Freescale Semiconductor Preliminary State During Reset Input On-Chip Regulator Disable — Tie this pin enable the on-chip regulator SS Tie this pin disable the on-chip regulator DD This pin is intended static DC signal from power-up to shut down ...
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... Port E GPIO — These two GPIO pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOE_PUR register. Example: GPIOE2, clear bit 2 in the GPIOE_PUR register. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... A12 23 (GPIOA4) A13 24 (GPIOA5) A14 25 (GPIOA6) A15 26 (GPIOA7) Freescale Semiconductor Preliminary State During Signal Description Reset In reset, Address Bus— A15 specify eight of the address lines for output is external program or data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus control ...
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... At reset, these pins default to the EMI Data Bus function. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOF_PUR register. Example: GPIOF9, clear bit 9 in the GPIOF_PUR register. 56F8356 Technical Data, Rev. 13 for further information on when this Freescale Semiconductor Preliminary ...
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... D14 136 (GPIOF7) D15 137 Input/ Output (GPIOF8) Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset In reset, Data Bus — D14 specify part of the data for external program output is or data memory accesses. disabled, pull-up is Most designs will want to change the DRV state to DRV = 1 instead of enabled using the default setting ...
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... CS0 is tri-stated when the external bus is inactive. CS0 resets to provide the PS function as defined on the 56F80x devices. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. To deactivate the internal pull-up resistor, clear bit 8 in the GPIOD_PUR register. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... Output GPIOD1 49 (CS3) TXD0 4 Output (GPIOE0) Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset In reset, Data Memory Select — This signal is actually CS1 in the EMI, output is which is programmed at reset for compatibility with the 56F80x DS disabled, signal asserted low for external data memory access. ...
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... JTAG/EOnCE port sampled on the rising edge internally of TCK and has an on-chip pull-up resistor. To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register. 56F8356 Technical Data, Rev. 13 Signal Description through a 2.2K resistor. DD Freescale Semiconductor Preliminary ...
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... Schmitt Input (TA0) Schmitt Input/ Output (GPIOC4) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Reset In reset, Test Data Output — This tri-stateable output pin provides a serial output is output data stream from the JTAG/EOnCE port driven in the disabled, shift-IR and shift-DR controller states, and changes on the falling pull-up is edge of TCK ...
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... TA3 — Timer A, Channel 3 Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is HOME0. To deactivate the internal pull-up resistor, clear bit 7 of the GPIOC_PUR register. 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... Input/ Output MISO0 131 Input/ Output (GPIOE6) Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, SPI 0 Serial Clock — In the master mode, this pin serves as an pull-up output, clocking slaved listeners. In slave mode, this pin serves as enabled the data clock input. Port E GPIO — ...
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... In the 56F8356, the default state after reset is PHASEA1. In the 56F8156, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOC_PUR register. 56F8356 Technical Data, Rev. 13 Part Freescale Semiconductor Preliminary ...
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... Schmitt Input/ Output (MOSI1) Schmitt Input/ Output (GPIOC1) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, Phase B1 — Quadrature Decoder 1, PHASEB input for decoder 1. pull-up enabled TB1 — Timer B, Channel 1 SPI 1 Master Out/Slave In — This serial data pin is an output from a master device and an input to a slave device ...
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... In the 56F8356, the default state after reset is HOME1. In the 56F8156, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 3 in the GPIOC_PUR register. 56F8356 Technical Data, Rev. 13 Part 6.5.8. Part 6.5.8. Freescale Semiconductor Preliminary ...
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... FaultA2 74 PWMB0 34 Output PWMB1 35 PWMB2 36 PWMB3 39 PWMB4 40 PWMB5 41 Freescale Semiconductor Preliminary State During Signal Description Reset In reset, PWMA0 - 5 — These are six PWMA outputs. output is disabled, pull-up is enabled Input, ISA0 - 2 — These three input current status pins are used for pull-up ...
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... Connect to a Output 0.1μF low ESR capacitor. Analog V — Analog Reference Voltage Low. This should normally REFLO Input be connected to a low-noise V 56F8356 Technical Data, Rev. 13 Part 6.5.8. Part 6.5.8. must be less REFH — Internal pins for voltage reference . SS Freescale Semiconductor Preliminary ...
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... Open Drain Output TC0 118 Schmitt Input/ Output (GPIOE8) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Analog ANB0 - 3 — Analog inputs to ADC B, channel 0 Input Analog ANB4 - 7 — Analog inputs to ADC B, channel 1 Input Analog Temperature Sense Diode — This signal connects to an on-chip ...
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... To deactivate the internal pull-up resistor, set the RESET bit in the SIM_PUDR register. See Output Reset Output — This output reflects the internal reset state of the chip. 56F8356 Technical Data, Rev. 13 Part 6.5.6 for details. Part 6.5.6 for details. Part 6.5.6 for details. Freescale Semiconductor Preliminary ...
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... Signal Name Pin No. Type EXTBOOT 112 Schmitt Input EMI_MODE 143 Schmitt Input Freescale Semiconductor Preliminary State During Signal Description Reset Input, External Boot — This input is tied to V pull-up boot from off-chip memory (assuming that the on-chip Flash enabled memory is not in a secure state). Otherwise tied to ground. ...
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... Detector Figure 3-1 OCCS Block Diagram Table 10-15. A recommended crystal oscillator circuit is shown 56F8356 Technical Data, Rev. 13 Figure 3-1 shows the ZSRC SYS_CLK2 Source to SIM PLLCOD Postscaler Postscaler CLK ÷ 1,2,4,8 Bus Interface LCK Loss of Reference Clock Interrupt Freescale Semiconductor Preliminary ...
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... A typical ceramic resonator circuit is shown in Refer to the supplier’s recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins. Freescale Semiconductor Preliminary EXTAL XTAL ...
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... XTAL R = 750 KΩ CLKMODE = Note: When using an external clocking source EXTAL with this configuration, the input “CLKMODE” should be high and the COHL bit in the OSCTL V register should be set 56F8356 Technical Data, Rev. 13 Figure 3-4. The external clock Freescale Semiconductor Preliminary ...
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... Table 4-1 Chip Memory Configurations On-Chip Memory 56F8356 Program Flash 256KB Data Flash 8KB Program RAM 4KB Freescale Semiconductor Preliminary Table Table 4-1. 56F8156 256KB Erase / Program via Flash interface unit and word writes to CDBW — Erase / Program via Flash interface unit and word writes to CDBW. ...
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... Mode 0 – Internal Boot; EMI is configured to use 16 address lines Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is determined by the state of the EMI_MODE pin Chip Operating Mode 56F8356 Technical Data, Rev. 13 Use Restrictions 4-2. Table 4-4 shows the memory Freescale Semiconductor Preliminary ...
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... Two independent program flash blocks allow one to be programmed/erased while executing from another. Each block must have its own mass erase. 4.3 Interrupt Vector Table Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is Freescale Semiconductor Preliminary Mode ...
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... P:$12 OnCE Trace Buffer P:$14 OnCE Transmit Register Empty P:$16 OnCE Receive Register Full Reserved P:$1C SW Interrupt 2 P:$1E SW Interrupt 1 P:$20 SW Interrupt 0 P:$22 IRQA P:$24 IRQB Reserved P:$28 Low-Voltage Detector (power sense) 56F8356 Technical Data, Rev. 13 Part Freescale Semiconductor Preliminary ...
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... SCI1 46 0-2 DEC1 47 0-2 DEC1 48 0-2 DEC0 49 0-2 DEC0 50 0-2 Freescale Semiconductor Preliminary Vector Base Interrupt Function Address + P:$2A PLL P:$2C FM Access Error Interrupt P:$2E FM Command Complete P:$30 FM Command, data and address Buffers Empty Reserved P:$34 FLEXCAN Bus Off P:$36 ...
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... ADC B Conversion Compete / End of Scan P:$94 ADC A Conversion Complete / End of Scan P:$96 ADC B Zero Crossing or Limit Error P:$98 ADC A Zero Crossing or Limit Error P:$9A Reload PWM B P:$9C Reload PWM A P:$9E PWM B Fault P:$A0 PWM A Fault P:$A2 SW Interrupt LP 56F8356 Technical Data, Rev (Continued) Freescale Semiconductor Preliminary ...
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... Flash Memory (FM) map on the system bus. The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides Freescale Semiconductor Preliminary Table 4-6 Data Memory Map ...
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... Technical Data, Rev. 13 Data Memory FM_BASE + $14 Banked Registers Unbanked Registers FM_BASE + $00 8KB Note: Data Flash is NOT available in the 56F8156 device. Sector Size Page Size bits 512 x 16 bits 256 x 16 bits 256 x 16 bits bits 256 x 16 bits Freescale Semiconductor Preliminary ...
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... OCR (bits) X:$FF FFFC OCLSR (8 bits) X:$FF FFFD OTXRXSR (8 bits) X:$FF FFFE OTX / ORX (32 bits) X:$FF FFFF OTX1 / ORX1 Freescale Semiconductor Preliminary Table 4-8 EOnCE Memory Map Reserved External Signal Control Register Reserved Breakpoint Unit [0] Counter Reserved Breakpoint 1 Unit [0] Mask Register ...
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... GPIOB X:$00 F300 GPIOC X:$00 F310 GPIOD X:$00 F320 56F8356 Technical Data, Rev. 13 Table Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 Freescale Semiconductor Preliminary ...
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... Address Offset CSBAR 0 $0 CSBAR 1 $1 CSBAR 2 $2 CSBAR 3 $3 CSBAR 4 $4 CSBAR 5 $5 CSBAR 6 $6 CSBAR 7 $7 Freescale Semiconductor Preliminary Prefix Base Address GPIOE X:$00 F330 GPIOF X:$00 F340 SIM X:$00 F350 LVI X:$00 F360 FM X:$00 F400 FC X:$00 F800 (EMI_BASE = $00 F020) ...
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... Freescale Semiconductor Preliminary ...
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... TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP Freescale Semiconductor Preliminary (TMRA_BASE = $00 F040) Address Offset Register Description $7 Status and Control Register $8 Comparator Load Register 1 $9 Comparator Load Register 2 $A Comparator Status and Control Register Reserve ...
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... Status and Control Register $8 Comparator Load Register 1 $9 Comparator Load Register 2 $A Comparator Status and Control Register Reserved $10 Compare Register 1 $11 Compare Register 2 $12 Capture Register $13 Load Register $14 Hold Register $15 Counter Register $16 Control Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... TMRB2_CMPLD1 TMRB2_CMPLD2 TMRB2_COMSCR TMRB3_CMP1 TMRB3_CMP2 TMRB3_CAP TMRB3_LOAD TMRB3_HOLD TMRB3_CNTR TMRB3_CTRL TMRB3_SCR TMRB3_CMPLD1 TMRB3_CMPLD2 TMRB3_COMSCR Freescale Semiconductor Preliminary (TMRB_BASE = $00 F080) Address Offset Register Description $17 Status and Control Register $18 Comparator Load Register 1 $19 Comparator Load Register 2 $1A Comparator Status and Control Register Reserved ...
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... Status and Control Register $18 Comparator Load Register 1 $19 Comparator Load Register 2 $1A Comparator Status and Control Register Reserved $20 Compare Register 1 $21 Compare Register 2 $22 Capture Register $23 Load Register $24 Hold Register $25 Counter Register $26 Control Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... Quad Timer D is NOT available in the 56F8156 device Register Acronym TMRD0_CMP1 TMRD0_CMP2 TMRD0_CAP TMRD0_LOAD TMRD0_HOLD TMRD0_CNTR TMRD0_CTRL TMRD0_SCR TMRD0_CMPLD1 TMRD0_CMPLD2 TMRD0_COMSCR Freescale Semiconductor Preliminary (TMRC_BASE = $00 F0C0) Address Offset $27 Status and Control Register $28 Comparator Load Register 1 $29 Comparator Load Register 2 $2A Comparator Status and Control Register Reserved ...
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... Status and Control Register $28 Comparator Load Register 1 $29 Comparator Load Register 2 $2A Comparator Status and Control Register Reserved $30 Compare Register 1 $31 Compare Register 2 $32 Capture Register $33 Load Register $34 Hold Register $35 Counter Register 56F8356 Technical Data, Rev. 13 Register Description Freescale Semiconductor Preliminary ...
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... PWMA_PWMCM PWMA_PWMVAL0 PWMA_PWMVAL1 PWMA_PWMVAL2 PWMA_PWMVAL3 PWMA_PWMVAL4 PWMA_PWMVAL5 PWMA_PMDEADTM PWMA_PMDISMAP1 PWMA_PMDISMAP2 PWMA_PMCFG PWMA_PMCCR PWMA_PMPORT PWMA_PMICCR Freescale Semiconductor Preliminary (TMRD_BASE = $00 F100) Address Offset $36 Control Register $37 Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 $3A Comparator Status and Control Register (PWMA_BASE = $00 F140) ...
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... Disable Mapping Register 2 $F Configure Register $10 Channel Control Register $11 Port Register $12 PWM Internal Correction Control Register (DEC0_BASE = $00 F180) Address Offset Register Description $0 Decoder Control Register $1 Filter Interval Register $2 Watchdog Time-out Register $3 Position Difference Counter Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... DEC1_DECCR DEC1_FIR DEC1_WTR DEC1_POSD DEC1_POSDH DEC1_REV DEC1_REVH DEC1_UPOS DEC1_LPOS DEC1_UPOSH DEC1_LPOSH DEC1_UIR DEC1_LIR DEC1_IMR Freescale Semiconductor Preliminary (DEC0_BASE = $00 F180) Address Offset Register Description $4 Position Difference Counter Hold Register $5 Revolution Counter Register $6 Revolution Hold Register $7 Upper Position Counter Register $8 Lower Position Counter Register ...
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... IRQ Pending Register 0 $12 IRQ Pending Register 1 $13 IRQ Pending Register 2 $14 IRQ Pending Register 3 $15 IRQ Pending Register 4 $16 IRQ Pending Register 5 Reserved $1D Interrupt Control Register (ADCA_BASE = $00 F200) Address Offset Register Description $0 Control Register 1 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... ADCA_LLMT 2 ADCA_LLMT 3 ADCA_LLMT 4 ADCA_LLMT 5 ADCA_LLMT 6 ADCA_LLMT 7 ADCA_HLMT 0 ADCA_HLMT 1 ADCA_HLMT 2 ADCA_HLMT 3 ADCA_HLMT 4 ADCA_HLMT 5 ADCA_HLMT 6 ADCA_HLMT 7 Freescale Semiconductor Preliminary (ADCA_BASE = $00 F200) Address Offset Register Description $1 Control Register 2 $2 Zero Crossing Control Register $3 Channel List Register 1 $4 Channel List Register 2 $5 Sample Disable Register ...
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... Limit Status Register $8 Zero Crossing Status Register $9 Result Register 0 $A Result Register 1 $B Result Register 2 $C Result Register 3 $D Result Register 4 $E Result Register 5 $F Result Register 6 $10 Result Register 7 $11 Low Limit Register 0 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... ADCB_OFS 4 ADCB_OFS 5 ADCB_OFS 6 ADCB_OFS 7 ADCB_POWER ADCB_CAL Table 4-22 Temperature Sensor Register Address Map Temperature Sensor is NOT available in the 56F8156 device Register Acronym TSENSOR_CNTL Freescale Semiconductor Preliminary (ADCB_BASE = $00 F240) Address Offset Register Description $12 Low Limit Register 1 $13 Low Limit Register 2 $14 Low Limit Register 3 ...
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... F290) Address Offset Register Description $0 Baud Rate Register $1 Control Register Reserved $3 Status Register $4 Data Register (SPI0_BASE = $00 F2A0) Address Offset Register Description $0 Status and Control Register $1 Data Size Register $2 Data Receive Register $3 Data Transmitter Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... OSCTL Table 4-29 GPIOA Registers Address Map Address Offset Register Acronym $0 GPIOA_PUR $1 GPIOA_DR $2 GPIOA_DDR $3 GPIOA_PER $4 GPIOA_IAR Freescale Semiconductor Preliminary (SPI1_BASE = $00 F2B0) Address Offset Register Description $0 Status and Control Register $1 Data Size Register $2 Data Receive Register $3 Data Transmitter Register (COP_BASE = $00 F2C0) Address Offset ...
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... EMI address at reset 0000 for all other cases. See Table 4-4 for details 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 00FF — Reset Value 0 x 07FF 0 x 0000 0 x 0000 0 x 07FF Freescale Semiconductor Preliminary ...
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... GPIOD_IPOLR GPIOD_IPR GPIOD_IESR GPIOD_PPMODE GPIOD_RAWDATA Table 4-33 GPIOE Registers Address Map Register Acronym Address Offset GPIOE_PUR GPIOE_DR GPIOE_DDR GPIOE_PER GPIOE_IAR Freescale Semiconductor Preliminary (GPIOC_BASE = $00 F310) Register Description $4 Interrupt Assert Register $5 Interrupt Enable Register $6 Interrupt Polarity Register $7 Interrupt Pending Register $8 Interrupt Edge-Sensitive Register ...
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... Technical Data, Rev. 13 Reset Value 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 3FFF — Reset Value 0 x FFFF 0 x 0000 0 x 0000 0 x FFFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x FFFF — Freescale Semiconductor Preliminary ...
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... Table 4-36 Power Supervisor Registers Address Map Register Acronym LVI_CONTROL LVI_STATUS Table 4-37 Flash Module Registers Address Map Register Acronym FMCLKD FMMCR FMSECH FMSECL Freescale Semiconductor Preliminary (SIM_BASE = $00 F350) Address Offset Register Description $0 Control Register $1 Reset Status Register $2 Software Control Register 0 ...
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... Free-Running Timer Register $6 Maximum Message Buffer Configuration Register Reserved $8 Receive Global Mask High Register $9 Receive Global Mask Low Register $A Receive Buffer 14 Mask High Register $B Receive Buffer 14 Mask Low Register $C Receive Buffer 15 Mask High Register 56F8356 Technical Data, Rev. 13 Register Description Freescale Semiconductor Preliminary ...
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... FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB2_CONTROL FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA FCMB2_DATA FCMB2_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $D Receive Buffer 15 Mask Low Register Reserved $10 Error and Status Register $11 Interrupt Masks 1 Register $12 Interrupt Flags 1 Register $13 Receive and Transmit Error Counters Register ...
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... Message Buffer 5 Data Register $6E Message Buffer 5 Data Register Reserved $70 Message Buffer 6 Control / Status Register $71 Message Buffer 6 ID High Register $72 Message Buffer 6 ID Low Register $73 Message Buffer 6 Data Register $74 Message Buffer 6 Data Register $75 Message Buffer 6 Data Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB10_CONTROL FCMB10_ID_HIGH FCMB10_ID_LOW FCMB10_DATA FCMB10_DATA FCMB10_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $76 Message Buffer 6 Data Register Reserved $78 Message Buffer 7 Control / Status Register $79 Message Buffer 7 ID High Register $7A Message Buffer 7 ID Low Register ...
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... Message Buffer 13 Data Register $AC Message Buffer 13 Data Register $AD Message Buffer 13 Data Register $AE Message Buffer 13 Data Register Reserved $B0 Message Buffer 14 Control / Status Register $B1 Message Buffer 14 ID High Register $B2 Message Buffer 14 ID Low Register $B3 Message Buffer 14 Data Register 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to service this interrupt. 5.2 Features The ITCN module design includes these distinctive features: Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description ...
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... Interrupt Vector Table Contents. 1 Permitted Exceptions SR[8] 0 Priorities Priorities Priorities Priority 3 Current Interrupt 1 Priority Level No Interrupt or SWILP Priority 0 Priority 1 Priorities 56F8356 Technical Data, Rev. 13 Masked Exceptions None Priority 0 Priorities 0, 1 Priorities Required Nested Exception Priority Priorities Priorities Priorities 2, 3 Priority 3 Freescale Semiconductor Preliminary ...
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... FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector adddress and not a JSR, the core starts its fast interrupt handling. Freescale Semiconductor Preliminary Part 5.6.30.2 56F8356 Technical Data, Rev. 13 ...
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... Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the 80 any0 Level 0 82 -> Priority Encoder any3 Level 3 IACK 82 -> Priority Encoder 56F8356 Technical Data, Rev. 13 INT VAB CONTROL IPIC SR[9:8] PIC_EN Freescale Semiconductor Preliminary ...
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... IRQP2 $13 IRQP3 $14 IRQP4 $15 IRQP5 $16 Reserved $17 ICTL $1D Freescale Semiconductor Preliminary Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F1A0) Register Name Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Interrupt Priority Register 7 ...
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... ADCB_CC IPL FAST INTERRUPT FAST INTERRUPT 0 VECTOR ADDRESS HIGH FAST INTERRUPT FAST INTERRUPT 1 VECTOR ADDRESS HIGH IRQB IRQA 1 IRQB STATE STATE INT_DIS EDG Freescale Semiconductor TRBUF IPL IRQA IPL 0 0 GPIOC IPL TMRC1 IPL TMRA1 IPL 1 PEND- 1 ING [81] IRQA EDG Preliminary ...
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... IRQ is priority level 2 • IRQ is priority level 3 5.6.1.4 Reserved—Bits 9–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $ Read Write RESET Figure 5-4 Interrupt Priority Register 1 (IPR1) Freescale Semiconductor Preliminary STPCNT IPL ...
Page 84
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through disabled by default. • IRQ disabled (default) • IRQ is priority level 1 • IRQ is priority level 2 • IRQ is priority level 3 84 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
Page 85
... Flash Memory Error Interrupt Priority Level (FMERR IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 Freescale Semiconductor Preliminary FMERR IPL LOCK IPL ...
Page 86
... External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 86 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
Page 87
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary GPIOF FCMSGBUF IPL ...
Page 88
... They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.4.8 Reserved—Bits 1–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 88 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
Page 89
... SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 Freescale Semiconductor Preliminary ...
Page 90
... Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through SCI1_RCV SCI1_RERR IPL IPL IPL 56F8356 Technical Data, Rev SCI1_TIDL SCI1_XMIT SPI0_XMIT IPL IPL IPL Freescale Semiconductor Preliminary 0 0 ...
Page 91
... IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.6.5 Reserved—Bits 7–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor Preliminary 56F8356 Technical Data, Rev. 13 Register Descriptions 91 ...
Page 92
... IRQ is priority level 1 • IRQ is priority level 2 5.6.7 Interrupt Priority Register 6 (IPR6) Base + $ Read TMRC0 IPL TMRD3 IPL Write RESET Figure 5-9 Interrupt Priority Register 6 (IPR6 TMRD2 IPL TMRD1 IPL TMRD0 IPL 56F8356 Technical Data, Rev DEC0_XIRQ DEC0_HIRQ IPL IPL Freescale Semiconductor Preliminary 0 0 ...
Page 93
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8356 Technical Data, Rev. 13 Register Descriptions 93 ...
Page 94
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 94 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
Page 95
... Timer B, Channel 1 Interrupt Priority Level (TMRB1 IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 Freescale Semiconductor Preliminary TMRB2 IPL ...
Page 96
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 96 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
Page 97
... Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary SCI0_TIDL ...
Page 98
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 98 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
Page 99
... Reload PWM B Interrupt Priority Level (PWMB_RL IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 Freescale Semiconductor Preliminary PWMA_RL ...
Page 100
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 100 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
Page 101
... Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-5. Freescale Semiconductor Preliminary ...
Page 102
... Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0 This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service 102 FAST INTERRUPT 0 VECTOR ADDRESS LOW 56F8356 Technical Data, Rev FAST INTERRUPT 0 VECTOR ADDRESS HIGH FAST INTERRUPT Freescale Semiconductor Preliminary ...
Page 103
... The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.18 IRQ Pending 0 Register (IRQP0) Base + $ Read Write RESET Figure 5-20 IRQ Pending 0 Register (IRQP0) Freescale Semiconductor Preliminary FAST INTERRUPT 1 VECTOR ADDRESS LOW ...
Page 104
... This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number 104 PENDING [32:17 PENDING [48:33 56F8356 Technical Data, Rev Freescale Semiconductor Preliminary ...
Page 105
... No IRQ pending for this vector number 5.6.23 IRQ Pending 5 Register (IRQP5) Base + $ Read Write RESET Figure 5-25 IRQ Pending Register 5 (IRQP5) 5.6.23.1 Reserved—Bits 96–82 This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing. Freescale Semiconductor Preliminary PENDING [64:49 ...
Page 106
... Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. • Required nested exception priority levels are • Required nested exception priority levels are • Required nested exception priority levels are 106 VAB INT_DIS 56F8356 Technical Data, Rev IRQB STATE IRQA STATE IRQB EDG Freescale Semiconductor Preliminary 0 IRQA EDG 0 ...
Page 107
... IRQA Edge Pin (IRQA Edg)—Bit 0 This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait modes automatically level-sensitive. • IRQA interrupt is a low-level sensitive (default) • IRQA interrupt is falling-edge sensitive Freescale Semiconductor Preliminary 56F8356 Technical Data, Rev. 13 Register Descriptions 107 ...
Page 108
... IRQs with fixed priorities: • Illegal Instruction • SW Interrupt 3 • HW Stack Overflow • Misaligned Long Word Access • SW Interrupt 2 • SW Interrupt 1 • SW Interrupt 0 • SW Interrupt LP These interrupts are enabled at their fixed priority levels. 108 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
Page 109
... Software-initiated reset • Four 16-bit registers reset only by a Power-On Reset usable for general purpose software control • System Control Register • Registers for software access to the JTAG ID of the chip Freescale Semiconductor Preliminary 56F8356 Technical Data, Rev. 13 Overview 21 clock cycles 109 ...
Page 110
... DSP56800E Reference Manual. Note: The OMR is not a Memory Map register directly accessible in code through the acronym OMR. 110 R/W R Figure 6-1 OMR 56F8356 Technical Data, Rev R/W R/W R/W R/W R Part 4.2 and Part 7 for detailed Freescale Semiconductor 0 MA R/W X Preliminary ...
Page 111
... SIM_PUDR Base + $A SIM_CLKOSR Base + $B SIM_GPS Base + $C SIM_PCE Base + $D SIM_ISALH Base + $E SIM_ISALL Freescale Semiconductor Preliminary Table 6-1 SIM Registers (SIM_BASE = $00 F350) Register Name Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID ...
Page 112
... EMI_ ONCE SW STOP_ MODE EBL0 RST DISABLE 0 0 SWR COPR EXTR POR CTRL JTAG 0 A21 A20 CLKDIS CLKOSEL PWM SCI1 SCI0 SPI1 SPI0 ISAL[23:22 EMI_ ONCE SW STOP_ MODE EBL RST DISABLE DISABLE Freescale Semiconductor 1 0 WAIT_ DISABLE PWM WAIT_ 0 Preliminary ...
Page 113
... Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this register. Freescale Semiconductor Preliminary 56F8356 Technical Data, Rev. 13 ...
Page 114
... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.3 SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3) Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality. 114 56F8356 Technical Data, Rev SWR COPR EXTR POR 0 0 Freescale Semiconductor Preliminary ...
Page 115
... Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID) 6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID) This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $601D. Base + $ Read Write RESET Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID) Freescale Semiconductor Preliminary FIELD ...
Page 116
... PWMA0—Bit 7 This bit controls the pull-up resistors on the FAULTA0, FAULTA1, and FAULTA2 pins. 6.5.6.10 Reserved—Bit 6 116 Figure 6-8) corresponds to a functional group of pins. See RESET IRQ XBOOT PWMB PWMA0 56F8356 Technical Data, Rev CTRL JTAG Freescale Semiconductor Preliminary ...
Page 117
... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.7.2 Alternate GPIOB Peripheral Function for A23 (A23)—Bit 9 • Peripheral output function of GPIOB7 is defined to be A23 • Peripheral output function of GPIOB7 is defined to be the oscillator_clock (MSTR_OSC, see Figure 3-4) Freescale Semiconductor Preliminary ...
Page 118
... GPIO Peripheral Select Register (SIM_GPS) The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate peripherals for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B (NOT available in the 56F8156 118 56F8356 Technical Data, Rev. 13 Figure 3-4) Freescale Semiconductor Preliminary ...
Page 119
... Table 6-2 Control of Pads Using SIM_GPS Control Pin Function GPIO Input 0 GPIO Output 0 Quad Timer Input / 1 2 Quad Decoder Input Quad Timer Output / 1 3 Quad Decoder Input Freescale Semiconductor Preliminary GPIOC_PER Register GPIO Controlled 0 1 SIM_ GPS Register 0 1 Control Registers 0 — — 1 — ...
Page 120
... GPIOC1 (C1)—Bit 1 This bit selects the alternate function for GPIOC1. • PHASEB1/TB1 (default) • MOSI1 120 Control Registers — 1 — — 1 — 56F8356 Technical Data, Rev Comments See SPI controls for determining the direction of each of the SPI pins Freescale Semiconductor Preliminary ...
Page 121
... FlexCAN Enable (CAN)—Bit 12 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.5 Decoder 1 Enable (DEC1)—Bit 11 Each bit controls clocks to the indicated peripheral. • Clocks are enabled Freescale Semiconductor Preliminary ...
Page 122
... Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.12 Serial Communications Interface 0 Enable (SCI0)—Bit 4 Each bit controls clocks to the indicated peripheral. • Clocks are enabled 122 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
Page 123
... If this register is set to something other than the top of memory (EOnCE register space) and the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions will be affected. Freescale Semiconductor Preliminary 56F8356 Technical Data, Rev. 13 Register Descriptions ...
Page 124
... This field represents the upper two address bits of the “hard coded” I/O short address. Base + $ Read Write RESET Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL) 124 “ Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction ISAL[21: 56F8356 Technical Data, Rev. 13 Instruction Portion ISAL[23:22 Freescale Semiconductor Preliminary ...
Page 125
... All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK = 60MHz. Freescale Semiconductor Preliminary Part 3 On-Chip Clock Synthesis Peripheral Clocks ...
Page 126
... A POR reset is first extended for 2 stabilization of the clock source, followed clock window in which SIM clocking is initiated 126 D Q D-FLOP D-FLOP C R Reset 56F8356 Technical Data, Rev. 13 56800E STOP_DIS Note: Wait disable circuit is similar Part 6.5.1. This procedure 21 clock cycles to permit Freescale Semiconductor Preliminary ...
Page 127
... Methods to block these are outlined in the next subsections. 7.2.1 Forced Operating Mode Selection At boot time, the SIM determines in which functional modes the device will operate. These are: • Internal Boot Mode • External Boot Mode Freescale Semiconductor Preliminary 56F8356 Technical Data, Rev. 13 Operation with Security Enabled 127 ...
Page 128
... FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values. 128 Figure 7-1. FM_CLKDIV[6] will map to the 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
Page 129
... TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence has completed. For details, see the JTAG Section in the 56F8300 Peripheral User Manual. Freescale Semiconductor Preliminary Flash Memory ...
Page 130
... There are six GPIO ports defined on the 56F8356/56F8156. The width of each port and the associated peripheral function is shown in shown in Table 8-3. 130 4-29 through Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is 56F8356 Technical Data, Rev. 13 4-34 define the actual reset values of Freescale Semiconductor Preliminary ...
Page 131
... Dedicated GPIO 2 pins - EMI CSn pins - EMI CSn - Not available in this package 2 pins - SCI1 2 pins - EMI CSn 3 pins - PWMB current sense Freescale Semiconductor Preliminary Peripheral Function Peripheral Function 56F8356 Technical Data, Rev. 13 Configuration Reset Function EMI Address EMI Address N/A ...
Page 132
... TMRC 1 pin - TMRC - Not available in this package 2 pins - Dedicated GPIO 2 pins - TMRD - Not available in this package 16 pins - EMI Data 132 Peripheral Function 56F8356 Technical Data, Rev. 13 Reset Function SCI0 EMI Address SPI0 TMRC N/A GPIO N/A EMI Data Freescale Semiconductor Preliminary ...
Page 133
... Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device GPIO Port GPIOA GPIOB Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 Peripheral 1 Peripheral 2 Peripheral 3 Peripheral 4 Peripheral 5 Peripheral 6 Peripheral 7 Peripheral 8 Peripheral ...
Page 134
... INDEX1 / TB2 / MISO1 3 Peripheral 4 Peripheral 5 Peripheral 6 Peripheral 7 Peripheral 8 Peripheral 9 Peripheral 10 Peripheral 56F8356 Technical Data, Rev. 13 Functional Signal Package PIn HOME1 / TB3 / SS1 PHASEA0 / TA0 139 PHASEB0 / TA1 140 INDEX0 / TA2 141 HOME0 / TA3 142 ISA0 113 ISA1 114 ISA2 115 Freescale Semiconductor Preliminary ...
Page 135
... Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device GPIO Port GPIOD GPIOE Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 GPIO 1 GPIO 2 N/A 3 N/A 4 N/A 5 N/A 6 Peripheral 7 Peripheral ...
Page 136
... Peripheral 3 Peripheral 4 Peripheral 5 Peripheral 6 Peripheral 7 Peripheral 8 Peripheral 9 Peripheral 10 Peripheral 11 Peripheral 12 Peripheral 13 Peripheral 14 Peripheral 15 Peripheral marketing representative 56F8356 Technical Data, Rev. 13 Functional Signal Package PIn D10 32 D11 133 D12 134 D13 135 D14 136 D15 137 authorized distributor Freescale Semiconductor for Preliminary ...
Page 137
... Table 10-1 Absolute Maximum Ratings Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Internal Logic Core Supply Voltage Input Voltage (digital) Input Voltage (analog) Output Voltage Freescale Semiconductor Preliminary are stress ratings only, and functional operation at the maximum CAUTION of any voltages = (V ...
Page 138
... J T STG T STG Min Typ 2000 — 200 — 500 — 56F8356 Technical Data, Rev. 13 Min Max Unit -0.3 6.0 V -40 125 °C -40 105 °C -40 150 °C -40 125 °C -55 150 °C -55 150 °C Max Unit — V — V — V Freescale Semiconductor Preliminary ...
Page 139
... TJ = Junction temperature TA = Ambient temperature Note: The 56F8156 device is guaranteed to 40MHz and specified to meet Industrial requirements only. Table 10-4 Recommended Operating Conditions (V = 0V, V REFLO Characteristic Supply voltage Freescale Semiconductor Preliminary Table 10-3 Thermal Characteristics Comments Symbol R θJA R θJMA Four layer board (2s2p) R θ ...
Page 140
... V +0.3 DDA -0.3 — 0.8 — — -4 — — -8 — — -12 — — 4 — — 8 — — 12 -40 — 125 -40 — 105 10,000 — — Cycles 10,000 — — Cycles 15 — — Years Freescale Semiconductor Preliminary Unit MHz °C °C ...
Page 141
... Output Current High Impedance State Schmitt Trigger Input V Hysteresis Input Capacitance C (EXTAL/XTAL) Output Capacitance C (EXTAL/XTAL) Input Capacitance Output Capacitance C See Pin Groups in Table 10-1 Freescale Semiconductor Preliminary Notes Min 2.4 OH — Pin Groups — Pin Group10 IH I Pin Group 13 — ...
Page 142
... External Clock is off 0μA 145μA • All peripheral clocks are off • ADC powered off • PLL powered off 56F8356 Technical Data, Rev. 13 Typ Max Units 1.8 1.9 V 2.14 — V 2.7 — V μA 110 130 Test Conditions Freescale Semiconductor Preliminary ...
Page 143
... Load) Loaded Output Voltage (200 mA load) Line Regulation @ 250 mA load (V 33 ranges from 3.0 to 3.6) DD Short Circuit Current (output shorted to ground) Bias Current Power-down Current Short-Circuit Tolerance (output shorted to ground) Freescale Semiconductor Preliminary DD_ADC DD_OSC_PLL DD_IO 13μA 50mA 2.5mA 13μA 70μ ...
Page 144
... ACC R — 0.104 ES 56F8356 Technical Data, Rev. 13 Typical Max Unit 0 0. — 200 ps — 175 ps 1 μA 100 150 Max Unit — mV/°C 28 °C 128 °C 153 °C — V 3.6 V μA 10 μA 250 0 6.7 °C — °C / bit Freescale Semiconductor Preliminary ...
Page 145
... There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual for details. Program time is per 16-bit word in Flash memory. Two words at a time can be programmed within the Pro- gram Flash module contains two interleaved memories. Freescale Semiconductor Preliminary Table Figure 10-1 ...
Page 146
... Technical Data, Rev Typ Max Unit — 120 MHz — — — 10 — 90% 50% 10 fall rise Min Typ Max 4 8 8.4 160 — 260 — /2), please refer to the OCCS chapter in OUT Freescale Semiconductor Unit MHz MHz ms Preliminary ...
Page 147
... Sum of the applicable wait state controls. The “Wait State Controls” column of Table 10-16 shows the applicable controls for each parameter and the EMI chapter of the 56F8300 Peripheral User Manual details what each wait state field controls. Freescale Semiconductor Preliminary Symbol Min ...
Page 148
... Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 10-4 External Memory Interface Timing 148 the EMI quadrature clock is generated using both edges of the EXTAL t ARDA WAC t WRRD t DOH t DOS Data Out 56F8356 Technical Data, Rev ARDD t RDA t t RDRD RD t RDWR t RDD DRD Data In Freescale Semiconductor Preliminary ...
Page 149
... RD Deasserted to Address Invalid Address Valid to RD Deasserted Valid Input Data Hold after RD Deasserted RD Assertion Width Address Valid to Input Data Valid Address Valid to RD Asserted RD Asserted to Input Data Valid WR Deasserted to RD Asserted Freescale Semiconductor Preliminary Wait States Symbol D Configuration WWS=0 -1.477 t AWR WWS>0 -1 ...
Page 150
... DCAEO WWSS, WWSH 1.00 0.50 RWSH, WWSS, 3 MDAR 0.75 + DCAOE 1,2 Typical Unit See Figure Max — 10-5 — ns 10-5 64T ns 10-5 — ns 10-6 — ns 10-7 — — ns 10-7 — — ns 10-8 — — ns 10-9 — Freescale Semiconductor Unit Preliminary ...
Page 151
... The interrupt instruction fetch is visible on the pins only in Mode 3. RESET t RAZ A0–A15, D0–D15 Figure 10-5 Asynchronous Reset Timing IRQA, IRQB Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive) Freescale Semiconductor Preliminary Reset, Stop, Wait, Mode Select, and Interrupt Timing Typical Symbol Min t 1. ...
Page 152
... Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing 152 First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I/O t IRI t IF 56F8356 Technical Data, Rev. 13 First Interrupt Vector Instruction Fetch First Instruction Fetch Not IRQA Interrupt Vector Freescale Semiconductor Preliminary ...
Page 153
... Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Freescale Semiconductor Preliminary 1 Table 10-18 SPI Timing Symbol Min ELD — 25 ...
Page 154
... Table 10-18 SPI Timing (Continued) Symbol Min held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8356 Technical Data, Rev. 13 Max Unit See Figure 10-10, 10-11, — 9.7 ns 10-12, — 9 LSB in (ref Master LSB out t R Freescale Semiconductor 10-13 Preliminary ...
Page 155
... SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-11 SPI Master Timing (CPHA = 1) Freescale Semiconductor Preliminary SS is held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8356 Technical Data, Rev. 13 Serial Peripheral Interface (SPI) Timing ...
Page 156
... SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-12 SPI Slave Timing (CPHA = 0) 156 ELD Slave MSB out Bits 14– MSB in Bits 14–1 56F8356 Technical Data, Rev ELG Slave LSB out LSB in Freescale Semiconductor Preliminary ...
Page 157
... Figure 10-13 SPI Slave Timing (CPHA = 1) 10.11 Quad Timer Timing Characteristic Timer input period Timer input high / low period Timer output period Timer output high / low period 1. In the formulas listed the clock cycle. For 60MHz operation 16.67ns. 2. Parameters listed are guaranteed by design. Freescale Semiconductor Preliminary ...
Page 158
... Parameters listed are guaranteed by design. Phase A (Input) Phase B (Input) Figure 10-15 Quadrature Decoder Timing 158 P INHL OUTHL OUT Figure 10-14 Timer Timing Symbol Min 56F8356 Technical Data, Rev INHL P OUTHL 1, 2 Max Unit See Figure — ns 10-15 — ns 10-15 — ns 10- Freescale Semiconductor Preliminary ...
Page 159
... TXD SCI receive data pin (Input) 10.14 Controller Area Network (CAN) Timing Note: CAN is NOT available in the 56F8156 device. Characteristic Baud Rate Bus Wake Up detection 1. Parameters listed are guaranteed by design Freescale Semiconductor Preliminary Table 10-21 SCI Timing Min BR — 0.965/BR PW 0.965/BR PW ...
Page 160
... Figure 10-19 Test Clock Input Timing Diagram 160 T WAKEUP Table 10-23 JTAG Timing Symbol Min f DC SYS_CLK SYS_CLK — — TRST 1 )/2 56F8356 Technical Data, Rev. 13 Max Unit See Figure MHz 10-19 MHz 10-19 — ns 10-19 — ns 10-20 — ns 10- 10- 10-20 — ns 10- Freescale Semiconductor Preliminary ...
Page 161
... Figure 10-20 Test Access Port Timing Diagram TRST (Input) 10.16 Analog-to-Digital Converter (ADC) Parameters Characteristic Input voltages Resolution 1 Integral Non-Linearity Differential Non-Linearity Monotonicity ADC internal clock Conversion range ADC channel power-up time Freescale Semiconductor Preliminary t DS Input Data Valid TRST Figure 10-21 TRST Timing Diagram ...
Page 162
... AIC 1 — t cycles AIC 5 — pF — — 1 — — mA μ +/- .004 +/- .015 — +/- 15 +/- 35 mV Figure 10-22 — LSBs 0.010380 — — -31.7 — — -60 — — V REFLO 64.6 — db 59.1 — db 60.6 — db 61.1 — db 9.6 — Bits Freescale Semiconductor Preliminary 3 3 ...
Page 163
... Although not guaranteed believed that calibration will produce results similar to those shown above for any population of parts including those which represent processing and temperature extremes. Freescale Semiconductor Preliminary = 0.60V and 2.70V in 56F8356 Technical Data, Rev ...
Page 164
... Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf 164 / 2, while the other charges to the analog input voltage. When the REFH REFH REFLO S2 2 56F8356 Technical Data, Rev The switches switch REFH REFH S 1pF Freescale Semiconductor Preliminary ...
Page 165
... Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. in the IO cells as a function of capacitive load. In these cases: TotalPower = Σ((Intercept +Slope*Cload)*frequency/10MHz) Freescale Semiconductor Preliminary 2 *F CMOS power dissipation corresponding to the Intercept 1 ...
Page 166
... For instance, if there is a total of 8 PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. 166 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
Page 167
... D10 GPIOB0 PWMB0 37 PWMB1 PWMB2 Figure 11-1 Top View, 56F8356 144-Pin LQFP Package Freescale Semiconductor Preliminary Figure 11-1 shows the package outline for the 144-pin LQFP, 56F8356 Technical Data, Rev. 13 56F8356 Package and Pin-Out Information Table 11-1 lists the pin-out for the ...
Page 168
... ISA2 116 TD0 117 TD1 118 TC0 3 119 V DD_IO 120 TRST 121 TCK 122 TMS 123 TDI 124 TDO 125 126 CAN_TX 127 CAN_RX 128 V 2 CAP 129 SS0 130 SCLK0 131 MISO0 132 MOSI0 133 D11 Freescale Semiconductor Preliminary ...
Page 169
... This section contains package and pin-out information for the 56F8156. This device comes in a 144-pin Low-profile Quad Flat Pack (LQFP). Figure 11-3 shows the mechanical parameters for this package, and 144-pin LQFP. Freescale Semiconductor Preliminary Signal Name Pin No. Signal Name PWMA0 ...
Page 170
... ANB4 ANB3 109 ANB2 ANB1 ANB0 V SSA_ADC V DDA_ADC V REFH V REFP V REFMID V REFN V REFLO NC ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 CLKMODE RESET RSTO V DD_IO V 3 CAP EXTAL XTAL V DDA_OSC_PLL OCR_DIS Pin No. Signal Name 109 ANB5 110 ANB6 Freescale Semiconductor Preliminary ...
Page 171
... CAP DD_IO A10 57 22 A11 58 23 A12 59 24 A13 60 25 A14 61 26 A15 62 Freescale Semiconductor Preliminary Signal Name Pin No. Signal Name PWMB3 75 D3 PWMB4 76 D4 PWMB5 77 D5 TXD1 78 D6 RXD1 79 OCR_DIS DDA_OSC_PLL RD 81 XTAL PS 82 EXTAL CAP GPIOD0 84 V DD_IO ...
Page 172
... SSA_ADC NC 104 ANB0 V 105 ANB1 SS NC 106 ANB2 NC 107 ANB3 D2 108 ANB4 56F8356 Technical Data, Rev. 13 Pin No. Signal Name 135 D13 136 D14 137 D15 138 A0 139 PHASEA0 140 PHASEB0 141 INDEX0 142 HOME0 143 EMI_MODE 144 V SS Freescale Semiconductor Preliminary ...
Page 173
... D1/2 D TOP VIEW H A SIDE VIEW PLATING BASE b METAL 0. SECTION A-A ° (ROTATED 90 ) 144 PLACES Figure 11-3 144-pin LQFP Mechanical Information Freescale Semiconductor Preliminary 0. TIPS 109 108 E1/2 E/2 VIEW VIEW B 0.1 A 144X θ SEATING PLANE ...
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... (Ψ 174 , can be obtained from the equation C/W) . For instance, the user can change the size of the heat θCA ) can be used to determine the junction temperature with a JT 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary ...
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... The minimum bypass requirement is to place six 0.01–0.1μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the V /V pairs, including performance tolerances. Freescale Semiconductor Preliminary C)/W CAUTION of any ...
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... All circuitry, analog and digital, shares a common V 176 layers of the PCB with approximately 100μF, preferably with a high-grade , V REF DDA pins. bus SS 56F8356 Technical Data, Rev. 13 and and and V pins SSA pin and cannot DDA_OSC_PLL DD_CORE Freescale Semiconductor Preliminary (GND) voltage ...
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... REFMID V REFN V REFLO V SSA_ADC Ambient Temperature Order Number (MHz) Range 60 -40° 105° C MC56F8356VFV60 60 -40° 125° C MC56F8356MFV60 40 -40° 105° C MC56F8156VFV 60 -40° 105° C MC56F8356VFVE* 60 -40° 125° C MC56F8356MFVE* 40 -40° 105° C MC56F8156VFVE* 177 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...