C8051F335-GM Silicon Laboratories Inc, C8051F335-GM Datasheet - Page 183

• Manufacturer Part Number: C8051F335-GM
• Description: IC 8051 MCU 2KB FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F335-GM

• Program Memory Type: FLASH
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 20-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F330DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• No. Of I/o's: 17
• Ram Memory Size: 768Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Data Rom Size: 128 B
• Height: 0.88 mm
• Length: 4 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1451 - ADAPTER PROGRAM TOOLSTICK F330
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1269

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF2H
R/W
Bit7
TF2H: Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode,
this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2 interrupt is
enabled, setting this bit causes the CPU to vector to the Timer 2 interrupt service routine.
TF2H is not automatically cleared by hardware and must be cleared by software.
TF2L: Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. When this bit is
set, an interrupt will be generated if TF2LEN is set and Timer 2 interrupts are enabled. TF2L
will set when the low byte overflows regardless of the Timer 2 mode. This bit is not automat-
ically cleared by hardware.
TF2LEN: Timer 2 Low Byte Interrupt Enable.
This bit enables/disables Timer 2 Low Byte interrupts. If TF2LEN is set and Timer 2 inter-
rupts are enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
0: Timer 2 Low Byte interrupts disabled.
1: Timer 2 Low Byte interrupts enabled.
TF2CEN: Timer 2 Low-Frequency Oscillator Capture Enable.
This bit enables/disables Timer 2 Low-Frequency Oscillator Capture Mode. If TF2CEN is set
and Timer 2 interrupts are enabled, an interrupt will be generated on a falling edge of the
low-frequency oscillator output, and the current 16-bit timer value in TMR2H:TMR2L will be
copied to TMR2RLH:TMR2RLL. See
details.
0: Timer 2 Low-Frequency Oscillator Capture disabled.
1: Timer 2 Low-Frequency Oscillator Capture enabled.
T2SPLIT: Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
TR2: Timer 2 Run Control.
This bit enables/disables Timer 2. In 8-bit mode, this bit enables/disables TMR2H only;
TMR2L is always enabled in this mode.
0: Timer 2 disabled.
1: Timer 2 enabled.
UNUSED. Read = 0b. Write = don’t care.
T2XCLK: Timer 2 External Clock Select.
This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this bit
selects the external oscillator clock source for both timer bytes. However, the Timer 2 Clock
Select bits (T2MH and T2ML in register CKCON) may still be used to select between the
external clock and the system clock for either timer.
0: Timer 2 external clock selection is the system clock divided by 12.
1: Timer 2 external clock selection is the external clock divided by 8. Note that the external
oscillator source divided by 8 is synchronized with the system clock.
TF2L
R/W
Bit6
SFR Definition 18.8. TMR2CN: Timer 2 Control
TF2LEN
R/W
Bit5
TF2CEN
R/W
Bit4
T2SPLIT
Rev. 1.7
Section “13. Oscillators” on page 113
R/W
Bit3
TR2
R/W
Bit2
C8051F330/1/2/3/4/5
Bit1
—
(bit addressable)
R
T2XCLK
R/W
Bit0
for more
SFR Address:
00000000
Reset Value
0xC8
187